Random-Access Memory (RAM) CS429: Computer Organization and Architecture. SRAM and DRAM. Flash / RAM Summary. Storage Technologies

Transcription

1 Random-ccess Memory (RM) CS429: Computer Organization and rchitecture Dr. Bill Young Department of Computer Science University of Texas at ustin Key Features RM is packaged as a chip The basic storage unit is a cell (one bit per cell) Multiple RM chips form a. Last updated: July 5, 2018 at 11:56 CS429 Slideset 17: 1 CS429 Slideset 17: 2 SRM and DRM Flash RM Summary Static RM (SRM) Each cell stores a bit with a 6-transistor circuit. Retains value indefinitely, as long as kept powered (volatile). Relatively insensitive to disturbances such as electrical noise. Faster but more expensive than DRM. Dynamic RM (DRM) Each cell stores a bit with a capacitor and transistor. Value must be refreshed every ms (volatile). Sensitive to disturbances, slower and cheaper than SRM Flash RM (what s in your ipod and cell phone) Each cell stores 1 or more on a floating-gate capacitor Keeps state even when power is off (non-volatile). s cheap as DRM, but much slower Note that flash has characteristics of RM (random access), but also of ROM (non-volatile). It s often considered a hybrid of both. CS429 Slideset 17: 3 CS429 Slideset 17: 4

2 RM Summary Conventional DRM Organization DRM is typically organized as a d w array of d supercells of size w. 16 x 8 DRM chip RM Summary Type Trans. ccess Persist? Sensitive Cost pplications per bit time SRM 6 1X No No 100X cache DRM 1 10X No Yes 1X main Flash X Yes No 1X disk substitute (to CPU) 2 addr 8 data 0 1 rows 2 3 cols supercell (2, 1) internal row buffer CS429 Slideset 17: 5 CS429 Slideset 17: 6 Reading DRM Supercell (2, 1) Step 1(a): Row access strobe (RS) selects row 2. Step 1(b): Row copied from DRM array to row buffer. RS=2 2 addr 8 data 16 x 8 DRM chip 0 1 rows 2 3 cols internal row buffer Reading DRM Supercell (2, 1) Step 2(a): Column access strobe (CS) selects col 1. Step 2(b): Supercell (2, 1) copied from buffer to data lines, and eventually back to the CPU. (to CPU) supercell (2, 1) CS=1 2 addr 8 data supercell (2, 1) 16 x 8 DRM chip 0 1 rows 2 3 cols internal row buffer CS429 Slideset 17: 7 CS429 Slideset 17: 8

3 Memory Modules Nonvolatile Memories addr (row = i, col = j) DRM 0 : supercell (i, j) DRM MB module consisting of eight 8Mx8 DRMs DRM and SRM are volatile memories; they lose information if powered off. Nonvolatile memories retain their value even if powered off. The generic name is read-only (ROM). This is misleading because some ROMs can be read and modified. 64 bit quadword at main address Memory ROM Memory CS429 Slideset 17: 9 64 bit doubleword CS429 Slideset 17: 10 Connecting CPU and Memory Types of ROM Programmable ROM (PROM) Eraseable programmable ROM (EPROM) Electrically eraseable PROM (EEPROM) Flash is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. CPU chip Firmware: Program stored in a ROM Boot time code, BIOS (basic inputoutput system) Graphics cards, disk s IO Bridge main CS429 Slideset 17: 11 CS429 Slideset 17: 12

4 Memory Read Transaction (1) Memory Read Transaction (2) CPU places address on the. Main reads from the, retrieves word x, and places it on the. load operation: movl, load operation: movl, Put on main x main x Places x on the. CS429 Slideset 17: 13 CS429 Slideset 17: 14 Memory Read Transaction (3) Memory Write Transaction (1) CPU reads word x from the and copies it into register. CPU places address on. Main reads it and waits for the corresponding data word to arrive. x load operation: movl, y store operation: movl, Copy x to register main x main Place on CS429 Slideset 17: 15 CS429 Slideset 17: 16

5 Memory Write Transaction (2) Memory Write Transaction (3) CPU places data word y on the. Main reads data word y from the and stores it at address. y store operation: movl, y store operation: movl, main main y CPU places data word y on the Main reads y from the CS429 Slideset 17: 17 CS429 Slideset 17: 18 Disk Geometry Disk Geometry (Multiple-Platter View) ligned tracks form a cylinder. Readwrite heads move in unison so are all on the same cylinder at any one time. Disks consist of platters, typically each have two surfaces though not always. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. CS429 Slideset 17: 19 CS429 Slideset 17: 20

6 Disk Capacity Disk Zones Capacity: maximum number of that can be stored. Vendors express this in terms of gigabytes (GB), where 1GB = 10 9 bytes. Capacity is determined by these technology factors: Recording density (in): number of that can be squeezed into a 1 inch segment of a track. Track density (tracksin): number of tracks that can be squeezed into a 1 inch radial segment. real density (in 2 ): product of recording and track density. Modern disks partition tracks into disjoint subsets called recording zones. Each track in a zone has the same number of sectors, determined by the circumference of the innermost track. Each zone has a different number of sectorstrack. Why does this make sense? CS429 Slideset 17: 21 CS429 Slideset 17: 22 Computing Disk Capacity Disk Operation (Single-Platter View) Capacity = ( bytessector) (avg. sectorstrack) (trackssurface) (surfacesplatter) (plattersdisk) Example: 512 bytessector 300 sectorstrack (on average) 20,000 trackssurface 2 surfacesplatter 5 plattersdisk Capacity = = 30, 720, 000, 000 = 30.72GB The disk surface spins at a fixed rotational rage. The readwrite head is attached to the end of the arm and flies over the disk surface on a a very thin cushion of air (around 0.1 microns). By moving radially, the arm can position the readwrite head over any track. CS429 Slideset 17: 23 CS429 Slideset 17: 24

7 Reading a Sector Disk ccess Time To read a sector on a disk requires: Seek: the read head is moved to the proper track. Rotational latency: the desired sector must rotate to the read head. Data transfer: the sector is read as it rotates under the read head. Writing is the same. Which of these do you suppose is longest? The average time to access a target sector is approximately: Taccess = T seek +T rotation +T transfer Seek time (T seek ) Time to position heads over cylinder containing the target sector. verage T seek = 9ms Rotational latency (T rotation ) Time waiting for first bit of target sector to pass under readwrite head. verage T rotation = 12 1RPMs 60sec1min Transfer time (T transfer ) Time to read the in the target sector. verage T transfer = 1RPM 1(average sectorstrack) 60sec1min CS429 Slideset 17: 25 CS429 Slideset 17: 26 Disk ccess Time Example Disk ccess Time Key Points Given: Derived: Rotational rate: 7,200 RPM verage seek time: 9 ms verage sectorstrack: 400 verage T rotation : 12 (60sec7200RPM) 1000mssec = 4ms verage T transfer : RPM 1(400 sectorstrack) 1000mssec = 0.02ms Taccess: 9 ms + 4 ms ms Important points: ccess time is dominated by seek time and rotational latency. The first bit in a sector is the most expensive; the rest are basically free. SRM access time is about 4ns doubleword; DRM about 60ns. Disk is about 40,000 times slower than SRM, and 2,500 times slower than DRM. CS429 Slideset 17: 27 CS429 Slideset 17: 28

8 Logical Disk Blocks IO Bus Modern disks present a simpler abstract view of the complex sector geometry. The set of available sectors is modeled as a sequence of b-sized logical blocks (0,1,2,...). Mapping between logical blocks and actual (physical) sectors: Is maintained by a hardwarefirmware device called a disk. Converts requests for logical blocks into (surface, track, sector) triples. llows the to set aside spare cylinders for each zone. This accounts for the difference between formatted capacity and maximum capacity. CPU chip mouse USB keyboard graphics adapter monitor IO disk Disk main CS429 Slideset 17: 29 CS429 Slideset 17: 30 Reading a Disk Sector Solid State Drives (SSDs) Solid State Disk (SSD) 1 The CPU initiates a disk read by writing a command, logical block number, and destination address to a port (address) associated with the disk. 2 The disk reads the associated sector and performs a direct access (DM) transfer into main. 3 When the DM transfer completes, the disk notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU). Flash Flash translation layer Block 0 Block B 1 Page 0 Page 1... Pare P 1... Page 0 Page 1... Pare P 1 Requests to read and write logical blocks come across the IO to the Flash translation layer. Pages are 512KB to 4KB; blocks are 32 to 128 pages. Data is readwritten in units of pages. page can only be written after its block has been erased. block wears out after around 100,000 repeated writes. CS429 Slideset 17: 31 CS429 Slideset 17: 32

9 SSDs Performance Characteristics SSD vs. Rotating Disks Sequential read tput 250 MBs Sequential write tput 170 MBs Random read tput 140 MBs Random write tput 14 MBs Random read access 30 µs Random write access 300 µs Why are random writes so slow? Erasing a block is slow (around 1 ms). Write to a page triggers a copy of all useful pages in the block. Must find a used block (new block) and erase it. Write the page into the new block. Copy other pages from the old block to the new block. dvantages: No moving parts; faster, less power, more rugged. Disadvantages: Have the potential to wear out. This is mitigated by wear leveling logic in the flash translation layer. E.g., Intel X25 guarantees 1 petabyte (10 15 bytes) of random writes before they wear out. In 2010, they were about 100X more expensive. But by November, 2013 this has fallen to 10X. By February, 2015, this was about 2X. pplications: MP3 players, smart phones, laptops. They are beginning to appear in desktops and servers. CS429 Slideset 17: 33 CS429 Slideset 17: 34 Storage Trends CPU Clock Rates Year: :2010 SRM $MB 19.2K 2.9K access (ns) DRM $MB 8K K access (ns) typical size K 8K 125K Disk $MB M access (ms) typical size K 20K 160K 1.5M 1.5M Year: :2010 CPU Pentium P-III P-4 Core 2 Core i7 Clock MHz Cycle (ns) Cores Effective K Cycle time round 2003, was the inflection point in computer history when designers hit the Power Wall. Cores increased, but the clock rate actually decreased. CS429 Slideset 17: 35 CS429 Slideset 17: 36

10 CPU-Memory Gap CPU speed increases faster than speed, meaning that: is more and more a limiting factor on performance; increased importance for caching and similar techniques. CS429 Slideset 17: 37