CS311 Lecture 21: SRAM/DRAM/FLASH

Transcription

1 S 14 L CS311 Lecture 21: SRAM/DRAM/FLASH DARM part based on ISCA 2002 tutorial DRAM: Architectures, Interfaces, and Systems by Bruce Jacob and David Wang Jangwoo Kim (POSTECH) Thomas Wenisch (University of Michigan) Bruce Jacob (University of Maryland)

2 Announcement S 14 L Programming Projects - Project #2: Due: 6/22 (better?) Don t wait until your final exam Project grading : #1 (40%) + #2 (60%) Your Final Exam! - Double check: 6/20 or 6/21? - Covers everything, focusing more on stuff after midterm 2 Read - Chapter 6.3~6.5 (DISK, Flash), 6.9 (RAID)

3 S 14 L Review on SRAM (Static Random Access Memory)

4 Static RAM (SRAM) (1/2) S 14 L Static Random Access Memory - Cache - Register file - Read - Sense bitline difference Write - Overwrite bitlines using strong signals 1 Cell = 6 transistors (typical) 4 (two invertors) + 2 (switches)

5 Static RAM (SRAM) (2/2) S 14 L bitline n+m n m 2 n row select bit-cell array 2 n row x 2 m -col (n m to minmize overall latency) _bitline 2 m diff pairs sense amp and mux 1 Read Sequence (assume bitlines are precharged) 1. Address decode 2. Drive row select 3. Selected bit-cells drive bitlines (entire row is read together) 4. Diff. sensing and column select (data is ready) 5. Precharge all bitlines (for next read or write) How do you write select columns? Access latency dominated by steps 2, 3 Cycle time dominated by steps 2, 3, 5 - Step 2 proportional to 2 m - Step 3 and 5 proportional to 2 n usually encapsulated by synchronous (sometime pipelined) interface logic

6 S 14 L DRAM (Dynamic Random Access Memory)

7 Dynamic RAM (DRAM) S 14 L row enable _bitline capacitor Bits stored as charge in capacitor - Bit cell loses charge when read - Bit cell drains over time RAS n 2 n bit-cell array 2 n row x 2 m -col (n m to minmize overall latency) Requires periodic refresh - Performed by mem controller - Refresh interval 10 s of ms - DRAM unavailable during refresh CAS m 2 m sense amp and mux 1 A DRAM die comprises of multiple such arrays

8 SRAM vs DRAM S 14 L SRAM - Faster access using bit-differential sense Pre-charging required - Strong storage doesn t need refreshing - But, static power consumption due to Vdd to ground paths DRAM - Smaller cells higher density Refreshing required - Bit, dynamic power consumption due to refreshing

9 Basics: DRAM organization S 14 L One bit = One Capacitor Accessed by Word Line (row) d Bit Line (column)

10 Basics: Access Process (1/5) S 14 L (1) BUS TRANSMISSION

11 Basics: Access Process (2/5) S 14 L (2) (optional PRECHARGE) & ROW ACCESS

12 Basics: Access Process (3/5) S 14 L (3) COLUMN ACCESS

13 Basics: Access Process (4/5) S 14 L (4) DATA TRANSFER

14 Basics: Access Process (5/5) S 14 L (5) BUS TRANSMISSION

15 DRAM Latency S 14 L DRAM Latency = A + B + C + D + E + F A: Transaction request may be delayed in queue B: Transaction request sent to memory controller C: Transaction request converted as DRAM command sequences D: Commands sent to DRAM E: Access DRAM : E1 (CAS) or E2 (RAS+CAS) or E3 (PRE+RAS+CAS) F: Transaction sent back to CPU

16 Basics: Physical Organization S 14 L ECC (optional) This is per bank. Typical DRAMs have 2+ banks

17 S 14 L Rank: 64-bit wide independent access Usually, chipset limits the number of memory ranks supported.

18 DIMM, Rank, Bank S 14 L

19 How have DRAMs evolved? S 14 L

20 DRAM Evolutionary Tree S 14 L

21 Read Timing of Conventional DRAM S 14 L

22 S 14 L Read Timing of Fast Page Mode One row address, multiple column addresses Exploits page buffering (or Row Buffer)that DRAMs already require internally

23 S 14 L Read Timing of Extended Data Out (EDO) As in FPM But overlapped Column Address assert with Data Out

24 Read Timing of Burst EDO S 14 L CAS Strobe indicates proceed to next sequential column address

25 Synchronous DRAM (SDRAM) S 14 L Adding a clock allows faster transfers, eliminates CAS strobes

26 Real-World Design Issues? S 14 L

27 DRAM Architecture Design S 14 L

28 Clocking Skewing S 14 L

29 Two Different Clocks? S 14 L

30 Bus & Path Length Issues S 14 L Difficult to implement high-frequency & wide parallel buses.

31 Topology? S 14 L

32 S 14 L

33 S 14 L

34 DDR (Double Data Rate) = 2x data transfer per command S 14 L

35 S 14 L x data pumping using both rising & falling clock edges.

36 DDR vs DDR2 vsddr3 S 14 L (Single-rate) SDRAM vs DDR SDRAM - Double pumping of data at both rising and falling edges Nearly 2x bandwidth over SDRAM DDR vs DDR2 - Data bus can run at 2x speed of the memory clock ~2x bandwidth over DDR (or 4x bandwidth over single-rate SDRAM) DDR2 vs DDR3-1.8V to DDR2 1.5V to DDR3 ~30% less power consumption

37 DDR vs DDR2 vsddr3 S 14 L

38 DDR2, DDR3,..? S 14 L Typical multichip access (240pin) Little bit slower, but more stable & low power (240pin)

39 S 14 L Fully Buffered DIMM (FB-DIMM) from Intel Higher Bandwidth higher clocking possible due to short strong channels via AMB (advanced memory buffer) Higher Capacity support many DIMMs Fast DIMM-to-DIMM transfer using narrow channels via AMB

40 DRAM Memory Controller S 14 L

41 Memory Controller (1/2) S 14 L First-come-first-serve (FCFS) - Serves memory requests in arrival order - Does not distinguish between different threads or memory episodes - Favors memory-intensive threads - Does not exploit row-buffer locality - Does not exploit bank-level parallelism of threads First-ready FCFS (FR-FCFS) - Commonly implemented in existing controllers - Prioritize Row-hit requests over others maximum throughput Older requests over younger ones - Thread-unawareness starvation possible for low row-hit threads

42 Memory Controller (2/2) S 14 L Fair queuing memory scheduler (FQM) - Exploit the fair queuing algorithm from computer networks - Attempt to partition memory bandwidth equally among threads For each thread, in each bank, FQM keeps a counter called virtual time and increases this counter when a memory request of the thread is serviced. Prioritize early virtual times for fairness - Does not work well for non-memory intensive workloads - Does not exploit row-buffer locality

43 DRAM: naming (1/2) S 14 L Register exists between DRAM module and memory controller for less load to controller (1 cycle penalty robustness with many modules)

44 DRAM: naming (1/2) S 14 L (speed) Data rate = 333M transfers with DDR So, memory bus = 166 Mhz = 166 * 2^20 cycles / s (data) 2700 MB / s = 2700 * 8 * 2^20 bits / s 2700 * 8 / 166 = 128 bits / clock

45 DRAM: naming (2/2) S 14 L

46 DRAM: naming (2/2) S 14 L (speed) Data rate = 400M transfers with DDR2 So, memory bus = Mhz = 100 * 2^20 cycles / s (data) 3200 MB / s = 3200 * 8 * 2^20 bits / s 3200 * 8 / 100 = 200 bits / clock

47 FLASH Solid-State Storage S 14 L

48 FLASH S 14 L Electrically modifiable, non volatile storage First developed by Toshiba around 1980 Evolved from ROM and EEPROM devices Principle of operation Transistor with a second floating gate Floating gate can trap electrons Results in detectable change in V t Control gate Floating gate Source Drain

49 FLASH cell operation (case of NOR) S 14 L Erasing to logical 1 0V Programming (=writing) to logical 0 +12V up to 200A Open 12V 0V +12V Quantum tunneling Drains charge from FG Hot-electron injection traps charge in FG

50 FLASH cell operation (NOR) S 14 L Reading +5V The strength of flow current between source and gate tells us its logical value : 1 or 0 1=less resistance, fast turn on GND Turn on low Vt or High Vt? 0=strong resistance (due to FTL electrons), slow turn on Detect I on to read 0 or 1

51 FLASH Programming (NOR) S 14 L Programming Flash - Change (byte or word) logical value from 1 to 0 - Apply high voltage on control gate Electrons are collected on floating gate Hot-electron injection V t increases = switching on higher voltage = low current = 0 Erasing Flash - Discharge charges in floating gate (entire block!) back to 1s. - Apply high voltage on drain - Electron tunneling Due to block-level erasure, any write must perform expensive erasure first.

52 FLASH: NOR model S 14 L NOR flash Each cell connected to GND and bitline On WL activated, the connected cell pulls the bitline low Speed tells me the value. Random, word-level programming Read/write on word level However, erasure is still done at block level In-place memory // e.g., EPROM, ROM,.. NOR = even only single cell (1) can pull the bitline to 0

53 FLASH: NAND model S 14 L NAND flash All cells are connected to global GND in serialized manner All-one cells pulled up high + one cell pulled up just over Vt of erasure state current will flow only when target cell s state is also erasure state. Sequential, block-level programming Block = a group of pages Block : 16KB ~ 512KB // erasure granularity Page: 512B~4KB // read & program granularity Higher density // e.g., USB, SSD,.. NAND = all other cells should be 1 to pull the bitline to 0

54 Building memories from cells S 14 L From Jim Cooke, Micron

55 S 14 L FLASH technology comparison NAND + High Density + Fast Write, Erase - Serial access (slow read) NOR + Byte-level random access + Fast Reads - Extremely slow write, erase Used for mass storage Used for code ROMs

56 S 14 L FLASH Technology Comparison Gb/cm 2 $/Gb Act Idle Read Write Erase (mw) (mw) (ms) DRAM ns 55 ns - NOR Flash ns 1.6 us (2B) 3300 us (4K) 700 NAND Flash (SLC) NAND Flash (MLC) us 220 us us 680 us 3.3 NAND NOR Erase Block size 4K 8K / 64K R/W unit size 4K 16B / 2B Endurance Good news: Denser, cheaper, lower idle & active power Bad news: Slow erase, limited lifetime ( writes)

57 Issues in FLASH S 14 L Limitations - Block-granularity erasure 0 cell entire block erasure 1 cell Even NOR cannot offer random-access re-write nor erasure - Memory wearing Finite number of program-erasure cycles (a.k.a. P/E cycles) e.g., 1,000,000 P/E cycles before wear out (Micron SLC, 2008) Wear leveling Spread writes to each block Use spare blocks - Read disturbance Many reads on a NAND cell changes the value of neighbor cells Error Correction Code (ECC) required

58 Denser FLASH S 14 L SLC (single-level cell) vs MLC (multi-level cell) - SLC Two levels of current = 0 or 1 - MLC N levels of current = log (N) logical states e.g., 2-bit MLC requires four levels of current (=4 threshold voltages based on 4 different levels of charges collected on floating gate) ECC is more critical than in SLC

59 Solid State Disks (SSD) : FLASH based disk S 14 L From Todd Dinkelman, Micron

60 Solid State Disks (SSDs) I/O bus S 14 L Solid State Disk (SSD) Flash memory Block 0 Page 0 Page 1 Page P-1 Flash Translation Layer Requests to read and write logical disk blocks Block B-1 Page 0 Page 1 Page P-1 Pages: 512B to 4KB, Blocks: 32 to 128 pages Data read/written in units of pages. Page can be written only after its block has been erased A block wears out after 100,000 repeated writes.

61 SSD Advantages S 14 L From Todd Dinkelman, Micron

62 S 14 L From Hubbert Smith, Samsung

63 S 14 L From Hubbert Smith, Samsung

64 Question? S 14 L Announcements: finish programming projects! Reading: Handouts: