DynamIQ Processor Designs Using Cortex-A75 & Cortex-A55 for 5G Networks

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1 DynamIQ Processor Designs Using Cortex-A75 & Cortex-A55 for 5G Networks Jeff Maguire Senior Product Manager Infrastructure IP Product Management Arm 2017 Arm Limited Arm Tech Symposia 2017

2 Agenda 5G networks Ecosystem software to support Arm based deployments of network hardware Arm Cortex-A75 and Cortex-A55 Conclusions Arm Limited

3 5G Networks 2017 Arm Limited

4 What is fog computing? CLOUD FOG COMPUTING A system-level horizontal architecture that distributes computing, storage, and networking closer to users IoT/AI Autonomous Vehicles AR/VR Arm Limited

5G Dynamics Across the Network: Edge to Cloud Compute IoT, Automotive, Industrial, Medical S A C S C A C C S A S C C A Storage Storage Storage ion ion Acceleration

5 5G Dynamics Across the Network: Edge to Cloud Compute IoT, Automotive, Industrial, Medical S A C S C A C C S A S C C A Storage Storage Storage ion ion Acceleration Packet Flows Packet Flows Packet Flows Devices Access/Edge Edge Compute Core / DC 5G vs. LTE Latency 30-50x Throughput 100x Connections 100x Mobility 1.5x Arm Limited

6 Network/Wireless Infrastructure: Three Distinct Segments Two Distinct Approaches Typically standardized platform designs 5G Antenna MEC Core Network/Data Centre CPU Server Server Air Interface Processing Base Station Network And RAN Offload Network Offload Typically customized platform designs Arm Limited

7 Network/Wireless Infrastructure: Edge Access Packet processing / front end / edge design. Arm: Meet diverse needs with heterogeneous platforms Mix of latency, throughput and power Supplement sub-systems approach with accelerator offload. Sub-system/packet processing platform ASIC based designs and dedicated platforms Merchant Silicon from multiple suppliers CCIX and connection to FPGA technology Arm Limited 5G Antenna CPU Air Interface Processing Edge Network Architecture 5G Air Interface Management Antenna, RRH, DFE, Distributed Base Band, Multi-Access Compute Acceleration. IoT Gateway and End applications. Optimized power, performance, latency Hardware acceleration for advanced signal processing and terabit throughput. Base Station Customized platform designs

8 Network/Wireless Infrastructure: Core Network Leverage energy efficient Arm servers with specifics for network infrastructure Linaro Server group activity, VNF porting activity, OPNFV actions, AIDC, OSEC Server-like Architecture more efficient on Arm Core Network/Data Centre Standardized general purpose compute platforms on Arm Performance/Density/Scalibility Support dedicated offload through silicon/software. DPDK/ODP support 5G Network Hierarchy Design Multi-Access Edge Compute, Distributed Evolved Packet Core, Distributed Applications Processing, Distributed Content Delivery Application of virtualized/containerized workloads Control plane functions, content and applications delivery can use general purpose virtualized cloud computing. Server Network Offload Arm Limited

9 Network/Wireless Infrastructure: Mobile Edge Compute Workload optimized general purpose compute and accelerators for user plane processing. MEC Edge Compute Architecture MEC will be critical in meeting 5G goals Low latency, low power required E2E Automotive assisted driving, IoT and industrial use cases 5G network Slicing dependent Designs range from chassis, multi chip to SOC designs Server Network And RAN Offload Unique designs tailored to MEC form factor will prevail. Mix of: Core network needs (software driven, compute performance) Edge Network needs (Latency, throughput, power optimized) 5G network slicing power and latency Arm Limited

10 Linaro Segment Groups - Infrastructure Networking - LNG OSS for networking ODP crossplatform support for SoC accelerators Enterprise - LEG OSS for Arm servers Reduces fragmentation, cost, accelerates time to market for servers based on Arm Real Time Support Virtualization, Core isolation OpenDataPlane (ODP) OPNFV integration ATF/UEFI/ACPI KVM/Xen Armv8 optimization OpenJDK, Hadoop, OpenStack, Docker Arm Limited

Virtual Infrastructure Managers Virtualization and HAL

11 Networking-centric Ecosystem Enabling Deployments Key Applications, VNFs, and Middleware Operating System and Virtual Infrastructure Managers Virtualization and HAL Firmware & Network Boot ACPI OEMs and ODMs Arm SoC Arm Limited

WorksOnArm, and AIDC 12 2017 Arm Limited

Initiated and hosted by Arm Public vehicle

12 WorksOnArm, and AIDC Arm Limited WorksOnArm Initiated and hosted by Packet.net Public vehicle to engage open source developers and share software readiness AIDC Initiated and hosted by Arm Public vehicle to engage infrastructure developer community (H/W & S/W)

Pharos Labs Fully compliant NFVI software

announced replicating Arm NFVI platform in

Stack Arm reference platform Jump Server x86

13 Pharos Labs Fully compliant NFVI software platform April 2016: 1 st ARM-based OPNFV Lab by Enea VPN INTERNET VPN Gateway Router Orange Labs, China Mobile, and others to be announced replicating Arm NFVI platform in their labs POD Firewall Colorado Reference Stack Arm reference platform Jump Server x86 3x Control Nodes Complete Pharos ~1 cu. Ft. / 250W Marvell MACCHIATObin boards (Quad-CA72) Arm Limited Build Server ARM64 2x Compute Nodes

14 Cortex-A75 and Cortex-A Arm Limited

15 DMC-620 DMC-620 Scalable solutions from edge to core Scalable system configurations Access point 4 Cortex-A CPUs 256 Data center compute DMC-620 PCIe 100GbE DMC-620 Cortex-A Accelerator IO IO NIC-450 0MB System cache 128MB CPU CPU CPU CPU DMC-620 CPU CPU CPU CPU CoreLink CMN-600 System cache DMC GB/s Bandwidth 1 TB/s CoreLink CMN-600 CPU CPU CPU CPU DMC620 : dynamic memory controller CMN: coherent mesh network interconnect 1 DDR channels 8 CPU CPU CPU CPU DMC-620 DMC-620 DMC Arm Limited

16 New DynamIQ-based CPUs for new possibilities Arm Cortex-A75 Arm Cortex-A55 >50% more performance compared to current devices 2.5x higher power efficiency compared to current devices Estimated device performance using SPECINT2006, final device results may vary Comparison using Cortex-A72 at 2.4GHz vs Cortex-A75 at 3GHz Comparison using Cortex-A53 in 28nm devices vs Cortex-A55 in 16nm devices Arm Limited

17 New DynamIQ-based CPUs for new possibilities Arm Cortex-A75 Arm Cortex-A55 SPECint x SPECint x SPECfp x SPECfp x LMBench memcpy 1.30x LMBench memcpy 1.97x Baseline to Cortex-A72 Baseline to Cortex-A53 All comparisons at ISO process and frequency All comparisons at ISO process and frequency Arm Limited

Next-generation features Dot product and half-precision float for AI/ML processing. Virtualized Host Extensions (VHE) offering Type-2 hypervisor (KVM) performance improvements.

18 Next-generation features Dot product and half-precision float for AI/ML processing. Virtualized Host Extensions (VHE) offering Type-2 hypervisor (KVM) performance improvements. Cache stashing and atomic operations improves multicore networking performance and improves latency. Cache clean to persistence to support storage class memory. Infrastructure class RAS enhancement including data poisoning and improved error management Arm Limited

19 DynamIQ Shared Unit (DSU) Support for multiple performance domains Any mix of DynamIQ cores, up to four premium Core 0 Private L2 DynamIQ cluster 0-7 Cores DynamIQ Shared Unit (DSU) Core 7 Private L2 Improved performance with large private cache Streamlines traffic across bridges Snoop filter L3 Cache Asynchronous bridges Bus I/F ACP and peripheral port I/F Power Management Advanced power management features Supports large amounts of partitionable local memory Connection to high-performance interconnect, with stashing support Low latency interfaces for closely coupled accelerators Arm Limited

20 Level 3 cache partition in a networking application Infrastructure Process 1 = data plane Process 2 = control plane Packet processing data sent through low latency ACP interface Sensors or I/O agents Example configuration with two Core groups in a DynamIQ cluster Process 1 Process 2 Core0 Core1 Core2 Core3 Core4 Core5 Core6 Core7 Core group 1 Core group 2 L3 cache ACP Reserved for external accelerators via ACP Group 1 Group Arm Limited

21 Increasing performance through cache stashing Enables reads/writes into the shared L3 cache or per-core L2 cache. Allows closely coupled accelerators and I/O agents to gain access to core memory. AMBA 5 CHI and Accelerator Coherency Port (ACP) can be used for cache stashing. More throughput with Peripheral Port (PP) for acceleration, network, storage usecases. Core0 L1 cache L2 cache Snoop filter Accelerator or I/O Stash critical data to any cache level DynamIQ cluster 0 7 Cores DynamIQ Shared Unit (DSU) L3 Cache Asynchronous bridges Cortex-A CPU CPU CPU L2 L2 Cache L2 L2 Cache Cache L3 Cache Bus I/F Agile System Cache ACP and peripheral port I/F CoreLink CMN-600 Core7 L1 cache L2 cache Power Mngmt Cortex-A CPU CPU CPU L2 L2 Cache L2 L2 Cache Cache L3 Cache Agile System Cache Arm Limited DMC-620 DDR4 DMC-620 DDR4

22 Networking: Compute and packet-processing solution Build the right mix of compute High-performance Cortex-A75 High-efficiency throughput Cortex-A55 DSP, accelerators Data plane processing Throughput compute Optional local accelerators Control plane processing Performance compute Timing critical processing Scale CoreLink CMN-600 for application Cortex-A55 Level-3 Cache Local Accelerator Cortex-A75 Level-3 Cache DSP / Accel Access points: 2~5W Macro BTS: 20~30W Telecom server: 60~100W CoreLink CMN-600 Agile System Cache Agile System Cache DMC-620 DMC-620 PCIe Enet Multi-chiplet Multi-socket Accelerator Arm Limited Scalable coherent SoC memory system with partitionable affinity

23 DMC-600 DDR PCIe PCIe CML CML DMC-600 DDR Data center server blade: Maximize compute density Cortex-A75 can deliver 1.4x to 2.9x higher performance. DDR DMC-600 PCIe 100GbE DDR DMC-600 >1.4x performance with 32 core Cortex-A75 + CMN-600 vs. 32 core Cortex-A72 + CCN-512 DDR DMC-600 Cache Cache Cache Cache 2.9x performance with 64 core Cortex-A75 +CMN-600 Higher rate performance than competitive architectures per socket Cache Cache Cache Cache 1-1.5W/core enables sustained operation at maximum performance Power: 60W compute. DDR DMC-600 Cache Cache Cache Cache Cache Cache Cache Cache DMC-600 DMC-600 DDR DDR Arm Limited

24 Enabling 5G transformation Transition to 5G networks and new use cases is transforming network architectures. Requires efficient compute closer to the edge Mobile Edge Compute (MEC) nodes combine server-like design (software driven, high aggregate performance) with edge network needs (latency, throughput, power optimized) Software investments from Arm and ecosystem partners to enable real 5G deployment. Cortex-A75 & Cortex-A55 together with CMN and other Arm IP enable scalable design. Address the compute requirements across the network in a range of power budgets Arm Limited

25 Thank You! Danke! Merci! 谢谢! ありがとう! Gracias! Kiitos! Arm Limited

26 The Arm trademarks featured in this presentation are registered trademarks or trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. All other marks featured may be trademarks of their respective owners Arm Limited

DynamIQ Processor Designs Using Cortex-A75 & Cortex- A55 for 5G Networks

DynamIQ Processor Designs Using Cortex-A75 & Cortex- A55 for 5G Networks 2017 Arm Limited David Koenen Sr. Product Manager, Arm Arm Tech Symposia 2017, Taipei Agenda 5G networks Ecosystem software to support