Building blocks for 64-bit Systems Development of System IP in ARM

Transcription

1 Building blocks for 64-bit Systems Development of System IP in ARM Research University of York January 2015 Stuart Kenny stuart.kenny@arm.com 1

2 2 64-bit Mobile Devices

3 The Mobile Consumer Expects Something New Every Year Dual-core CPU performance 2011 >13 MPixel camera 2012 >5.0 inch 1080p 60fps screens 2013 ARMv8-A and shift to 64-bit 2014 Your next flagship devices 3

4 Why 64-bit in Mobile? Cleaner instruction set architecture Performance through architecture Hard-float ABI by default in ARMv8-A More registers, less stack spillage Cheaper function calls Up to 16x crypto acceleration Preparation for larger memory devices 4

5 Peak on-chip system bandwidth (GB/s) Increasing Demand for System Bandwidth >20 Mpixel cameras and 4K output Capture and screen frame rates Screen sizes and resolutions Year of device shipping 5

6 Designing Within an Energy and Thermal Envelope High-end feature rich gaming Video editing on the move SoC mobile power envelope 2.5-3W 4-5W 7W 6

7 Mobile Application Workloads Web Browsing Mobile users spend a high amount of time on a range of mobile applications*: 38% on web browsing and Facebook 32% on gaming 16% on audio, video and utility Power Power Power Time Gaming Common building blocks in workloads: Short bursts of high intensity Long periods of sustained high intensity Low intensity Time Audio Playback * Source: Flurry Analytics Time 7 Measured on a Quad Cortex-A7 Symmetric Multiprocessing platform

8 big.little Technology Heterogeneous Computing 2x higher performance vs. SMP* Up to 75% CPU power savings vs. SMP* Architecturally Identical Processors High performance tuned big cores Low power tuned LITTLE cores Hardware Coherency Cache Coherent Interconnect (CCI) L1 and L2 snooping between clusters Seamless & Automatic Task Allocation Interrupt Control big Cluster LITTLE Cluster L2 Cache L2 Cache Cache Coherent Interconnect Right Task on the Right Core Up to 40% SOC power savings** 8 * Quad Cortex-A15 Symmetrical Multiprocessing System (SMP) ** Measured across a set of casual games and common use-cases on an ARM Partner 4xCortex-A15.4xCortex-A7 big.little device

9 big.little is Mainstream Cortex-A15/A7 big.little in product in 2014 Mediatek MT8135, Samsung Exynos 5422, Allwinner A80 High-end mobile moving to A57 and A53 big.little Benefits for additional high-end performance, 64-bit Silicon expected in late e.g. Qualcomm Snapdragon 810, Exynos 7 Octa Global Task Scheduling is now a differentiation point HMP access to all cores 9

10 CoreLink CCI-400 System Coherency for 64-bit big.little High performance hub interconnect for smart phone and beyond 2 CPU clusters, 8 core GPU, DMC Performance and power efficiency with big.little Supporting Cortex-A53 and Cortex-A57 Integrated clock gating System level hardware coherency Full coherency for CPU I/O coherency for GPU Mature and silicon proven, over 30 licensees Quad Cortex-A57 L2 DDR Quad Cortex-A53 L2 CoreLink CCI-400 Cache Coherent Interconnect with AMBA 4 ACE Mali-GPU System and I/O First of a generation supporting multi-cluster coherency. We are actively working on the next generation CCI. 10

11 64-bit Mobile Sub-System Example Unified interrupts for complex processors ETM GIC-500 Cortex-A57 Cortex-A53 I/O Coherent Masters NIC-400 CCI-400 MMU-500 Mali T760 GPU Mali V500 NIC-400 MMU-500 Display Common memory view for all SoC components Hardware coherency enables big.little and simplifies software Optimized path to memory for best performance Configurable interconnect enables flexible system design STM Peripherals TZC-400 Memory System DMC rd Party: LPDDR3/4 Software Debug, Hardware Performance Trace DRAM 11

12 64-bit Mobile Sub-System Debug and Trace Real-time trace Run-control debug Performance Analysis Cross communication of events STM 12 ETM System & Software Trace Cortex-A57 GIC-500 PMU ETM Cortex-A53 Peripherals PMU Debugger access to peripherals I/O Coherent Masters NIC-400 CCI-400 MMU-500 Mali T760 GPU TZC-400 Memory System DMC rd Party: LPDDR3/4 Debugger access to memory DRAM Mali V500 CTM NIC-400 MMU-500 Display TPIU timestamp TMC Off-chip trace Selfhosted trace Event & trace correlation

13 13 64-bit Infrastructure Devices

14 Content in the Cloud Drives Intelligence in the Network Wide range of network performance and intelligence behaviors The Cloud / Data Center STB Rendering moving into network for greater UI possibilities Display Clients Content moving closer to user for better performance 14

15 Infrastructure Compute Challenges Networking and Datacenter Infrastructure requires solving diverse problems Heterogeneous platforms for diverse environments Data center to shopping center! Power efficiency and elasticity are always important Evolving compute problems Demanding performance/efficiency requirements Different cores for different problems Common SW Framework on heterogeneous compute platforms 15

16 Heterogeneous Compute Requirements Control Plane Processing Fast Event Processing Complex signalling Trend: Evolving Software Need: Efficient, High Compute Performance MAC Scheduling Real Time, Latency Driven Multiple core processing Trend: More Complexity (LTE-A, 5G) Need: High Compute, Low Latency Performance High Bandwidth, Low Latency Interconnect Wide Range of Implementations from Few to Many Coherent Devices Data Plane Processing Throughput driven, IO intensive Deterministic performance Trend: Higher packet rates Need: Small Cores at Maximum Efficiency Specialised Processing L1, Content Delivery, Security Diverse requirements Trend: Advanced modulation schemes Need: DSPs, Accelerators 16

17 Extending the ARM CoreLink Cache Coherent Network Family Cortex-A57 CoreLink CCN-502 High Performance, Small Footprint Cortex-A57 GIC-500 Cortex-A53 Cortex-A53 CoreLink CCN-502 Cache Coherent Network PCIe GbE DSP DSP DSP USB I/O Virtualisation CoreLink MMU-500 SATA NIC-400 Cortex-A57 Cortex-A53 Cortex-A57 Cortex-A53 CoreLink CCN-512 Maximize Compute Density GIC-500 Cortex-A57 Cortex-A53 Cortex-A57 Cortex-A53 Cortex CPU or CHI master ACE Cortex CPU or CHI master Cortex CPU or CHI master Cortex CPU or CHI master GbE DPI PCIe DPI PCIe Crypto AHB DSP DSP DSP I/O Virtualisation CoreLink MMU-500 USB SATA NIC MB L3 cache Snoop Filter CoreLink CCN-512 Cache Coherent Network 1-32MB L3 cache Snoop Filter Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Network Interconnect NIC-400 Flash SRAM GPIO PCIe Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Network Interconnect NIC-400 Flash SRAM Network Interconnect NIC-400 GPIO PCIe Up to 4 Clusters (16 cores) Small to Mid-Range Systems Up to 12 Clusters (48 cores) High-End Systems 2 new members extend the scalability of the CCN family Native AMBA 5 CHI interfaces providing high frequency, non-blocking data transfers End-to-end QoS and RAS Integrated Level 3 Cache and Snoop Filter 17

18 System Performance Scalable Efficient Interconnect for Compelling Solutions Cost-efficient Mid-range High-end CCN-512 CCN-508 0MB CCI-400 CCN-502 CCN-504 Level-3 Cache Size System Size AMBA 5 CHI AMBA 4 ACE 32MB DDR Bandwidth 20 GB/s 100 GB/s On-chip bandwidth 0.2 Tb/s 1.8 Tb/s 18

19 Scalable Platform for Diverse Processing Needs Cortex-A7 Cortex-A53 CCI-400 CCN-502 Cortex-A53 Cortex-A57 CCN-502 CCN-504 Cortex-A53 Cortex-A57 CCN-508 CCN-512 Cost-Efficient Power-Optimized 20 Mid-range Performance High Performance Networking and Server

20 Efficient Hardware-Assisted Virtualization Direct hardware access with MMU-500 Low latency interrupt delivery with GIC-500 Support for on-chip or off-chip peripherals 21

21 Infrastructure System Example GIC-500 Cortex-A57 Cortex-A57 Cortex-A53 Cortex-A53 CoreLink CCN-502 Cache Coherent Network 0-8MB L3 cache PCIe GbE DSP DSP DSP Snoop Filter USB I/O Virtualisation CoreLink MMU-500 SATA NIC-400 Unified interrupts for complex processors Common memory view for all SoC components Hardware coherency enables scaling and simplifies software Optimized path to memory for best performance Configurable interconnect enables flexible system design Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Memory DMC-520 x72 DDR Network Interconnect NIC-400 Flash SRAM GPIO PCIe Software Debug, Hardware Debug And System Profiling Design Environments for Rapid IP Configuration, Generation and Assembly 22

22 System IP for 64-bit Systems Summary 24

23 Mobile Picking Up the Pace and Reach Premium mobile expects something new every year ARMv8-A and shift to 64-bit Need for more performance in a constrained thermal envelope 25

24 Scalable Platforms for Diverse Processing Needs Cable Modem Set Top Box Optical Line Home Gateway Termination Optical Network Termination Cellular Remote Radio Head/Antenna Wi-Fi Access Point DSL Modem Femto BTS DSLAM Cellular Small Cell Base Stations Microwave Backhaul Media content web Mobile Broadband Access and Aggregation Scale out storage B-RAS Cloud Cellular Macro Cell RAN Base Stations Equipment Edge Router Core Router GGSN Optical Core Networking Equipment Edge Server SGSN Core Server CDN Evolved Packet Core HPC Web Scientific Compute Base Station NFV SDN Cloud CDN Storage Array Network XaaS Cloud 26

25 Debug and Trace Solutions for 64-bit Systems 27

26 Juno The First ARMv8-A 64-bit Software Development Target Juno Premium ARMv8-A software target platform Available now ARMv8-A System IP Interconnect, interrupts, virtualization, debug and trace 64 and 32-bit Software 64-bit applications support enabled 100% compatibility for 32-bit applications 28

27 arm.com/careers linkedin.com/company/arm twitter.com/armjobs facebook.com/armfans Play Your Part 29