HSMC Ethernet 2-Port 1588 Precision Timing

Transcription

1 Ethernet 2-Port 1588 Precision Timing PHY Daughter Board 1

2 Table of Contents 1 INTRODUCTION FEATURES BOARD DESCRIPTION BLOCK DIAGRAM BOARD COMPONENTS LEDs PHY Generic I/O (GPIO), J2, J Application () General Purpose I/O, J CLOCK DISTRIBUTION - MAC INTERFACE CLOCKING POWER-UP STRAP OPTIONS PHY 1 STRAP OPTIONS PHY 2 STRAP OPTIONS MDIO MANAGEMENT HIGH SPEED MEZZANINE CARD () CONNECTOR CONNECTOR PIN OUT TABLE PIN OUT DESCRIPTION PLCC-44 SOCKET PIN OUT FOR ALTERA STRATIX II GX PCIE BOARD PIN OUT FOR ALTERA CYCLONE-III STARTER KIT BOARD REFERENCES CONTACT

3 List of Tables Table 1: RJ45 LEDs... 8 Table 2: PHY 1 Power-Up Strap Options...11 Table 3: PHY 2 Power-Up Strap Options...12 Table 4: PHY MDIO Addresses...13 Table 5: Connector Pin out...14 Table 6: Connector Pin out Description...17 Table 7: PLCC-44 Socket Pin Description...20 Table 8: Interface Signals (Stratix II GX PCIe Board)...21 Table 9: Interface Signals (Cyclone-III Starter Kit Board)...23 List of Figures Figure 1: Daughter Board... 4 Figure 2: Board Block Diagram... 6 Figure 3: Board Components... 7 Figure 4: GPIO Connector (J2, J3)... 8 Figure 5: Application General Purpose I/O Connector (J4)... 9 Figure 6: Clock Distribution...10 Figure 7: Samtec ASP Figure 8: PLCC-44 Top View

4 1 Introduction The Nine Ways PhyworkX DP83640 Ethernet Development Kit provides an Ethernet PHY Daughter Board implementing two 10/100 Ethernet copper ports with high precision IEEE 1588 time synchronization support. The board implements two independent Ethernet interfaces with several system interface options and can be used in single and multi-channel applications. The daughter board implements a High Speed Mezzanine Card () connector to the main board that implements parallel RMII and provides the necessary 3.3V power supply. In combination with the MorethanIP/Nine Ways Ethernet Cores (e.g. MAC, Switch, IEEE 1588) the PHY daughter board can be used to quickly design, implement, prototype and test embedded Ethernet Telecom or Industrial applications with support for precise timing according to the IEEE 1588 standard. The board is optionally available with reference designs using a MAC, with support for IEEE1588, for precise time synchronization applications, or with a 3-port Switch application. The board can be used with any Altera (e.g. Arria GX, Stratix II GX, Cyclone III) or Nine Ways board that implements a connector. Figure 1: Daughter Board 4

5 2 Features Two High Performance National DP /100 Ethernet PHY o Integrated IEEE 1588 support with synchronizable timer o Auto negotiation for automatic speed selection o Automatic cable crossover configuration o Reduced Media Independent Interface (RMII) o PHY Management Interface (MDIO/MDC) for configuration/status 2x Standard Ethernet Copper RJ45 connector (10/100 Base-T) Status LEDs for current speed, link and traffic indications 4 General Purpose I/Os for timing event generation and capture 5 General Purpose I/Os available to the application 168pin High Speed Mezzanine Card () Connector to main board providing power supply and I/O interfaces Single 3.3V power supply from Connector 2.5V and 3.3V I/O interfaces support Example Reference Designs available for several Main boards upon request 5

6 Connector 4x2 Connector 4x2 Dual DP83640 Ethernet PHY Daughter Board 3 Board Description 3.1 Block Diagram The Board implements the copper line interfaces using a 2x RJ45 array with integrated magnetics. The MAC interfaces are available at the connector using 2.5V/3.3V LVTTL/LVCMOS signaling. RJ45 (integrated Transformer) RJ45 (integrated Transformer) Testsignals National PHY1 DP MHz National PHY2 DP83640 Testsignals 25MHz Refclk RMII General Purpose Connector 5x2 Optional OTP Device PLCC-44 Socket 3.3V Power Connector Figure 2: Board Block Diagram 1 6

7 3.2 Board Components Port0 Port1 genio Figure 3: Board Components 7

8 3.2.1 LEDs The RJ45 connector provides a green and orange LED on its front side individual per port. Table 1: RJ45 LEDs LED green (l) orange (r) Description LED_LINK from PHY: Lit when link up LED_SPEED from PHY: On in 100Mbps mode, Off in 10Mbps mode. Note: The PHY powers up in Mode 1 for the LEDs (see strap options). That is, the LEDs are showing the above information. Line activity is not visible in this mode as there is no separate activity LED. It is possible to configure the PHY to operate the LEDs in Mode 2 by writing into MDIO register 0x19 clearing bits 5,6. In this mode, the link led will be on when the link is established and then blink on activity PHY Generic I/O (GPIO), J2, J3 Each PHY provides several general-purpose I/O pins for event generation and event capture. Four of these (gpio1-4) are available on a 5x2 connector on the daughter board per PHY device. In addition, the gpio4 is also available at the connector. Gpio8 of the PHY is wired to only. clk_out of the PHY is wired to and to the connector (5x2) to PHY 1/2 gpio1 gpio2 gpio3 gpio4 clk_out GND GND GND GND GND gpio8 to Figure 4: GPIO Connector (J2, J3) 8

9 The Connector J2 is for Port 0; Connector J3 is for Port 1. Note: gpio9 is connected in-between both PHY devices exclusively to allow synchronization of the internal 1588 timers during operation Application () General Purpose I/O, J4 For arbitrary purposes a 5x2 connector (J4) provides 5 signals that can be used for any implementation specific function. The signals are available at the connector only. (5x2) to genio0 genio1 genio2 genio3 genio GND GND GND GND GND Figure 5: Application General Purpose I/O Connector (J4) 9

10 4 Clock Distribution - MAC Interface Clocking After power-up the PHYs are configured to implement parallel RMII MAC interfaces. PHY1 is configured in RMII master mode and is responsible to generate all necessary clocks for the 2nd PHY (PHY2) as well as the MAC interfaces. PHY1 needs a 25MHz clock reference on its X1 clock input, which must be provided by the application through the connector. The MAC interface is synchronous to the 50MHz reference clock provided by PHY1. PHY1 provides the RMII interface clock on its rx_clk and tx_clk outputs. The PHYs are configured (see Strap Options, see section 5.2) to provide the internal synchronized Clock Distribution IEEE 1588 clock on its clk_out pin, which is available to the for use by 1588 related functions of the application. gpio9 gpio9 25MHz ref X1 tx_clk clk_out National PHY 1 DP83640 (RMII Master) rx_clk 50MHz X1 clk_out National PHY 2 DP83640 (RMII Slave) PTP Clock 50MHz PTP Clock RMII RMII ref_clk_x1 clk_out_0 Connector clk_out_1 Reference from FPGA (25MHz) 50MHz Reference to MAC Figure 6: Clock Distribution Reference to FPGA for PTP time related logic (25MHz) 3 Note: gpio9 is connected in-between both PHY devices exclusively to allow synchronization of the internal 1588 timers of both devices during operation. 10

11 5 Power-Up Strap Options When the board powers up it is configured to the following settings. Each PHY has slightly different settings as they have different modes of operation. PHY 1 is configured in RMII Master Mode. PHY 2 is configured in RMII Slave Mode. 5.1 PHY 1 Strap Options PHY Address set to 1 Mode set to RMII Master Auto negotiation is enabled for all ports Automatic cable crossover is enabled for all ports The optional clk_out clock output of the PHY is enabled Refer to the DP83640 datasheet for full detail. The "wiring" column indicates what kind of strap-option is used on the pin: A wiring of 'pull-up' means a pull-up (2.2K to VCC) is wired. A wiring of 'pull-down' means a pull-down (2.2K to GND) is wired. A wiring of "nc" means that pin has no strapping resistor connected to it. Table 2: PHY 1 Power-Up Strap Options Strap Function Pin Pin# Wiring Value Setting/Note PHYAD0 COL 42 nc 1 PHYADDR=1 PHYAD1 RXD_3 43 nc 0 (=default) PHYAD2..4 RXD_2.._ nc 000 AN_EN LED_LINK 28 nc 1 Autoneg enable Note: LED must be wired to VCC AN1 LED_SPEED 27 nc 1 AN0 LED_ACT 26 nc 1 all modes CLK_OUT_EN GPIO1 21 pull-up 1 enable clock output FX_EN_Z RX_ER 41 nc 1 disable FX mode LED_CFG CRS 40 nc 1 mode1 MII_MODE RX_DV 39 pull-up 1 RMII Mode PCF_EN GPIO2 22 nc 0 RMII_MAS TXD_3 6 pull-up 1 enable RMII master mode 11

12 5.2 PHY 2 Strap Options Dual DP83640 Ethernet PHY Daughter Board PHY Address set to 3 Mode set to RMII Slave Auto negotiation is enabled for all ports Automatic cable crossover is enabled for all ports The optional clk_out clock output of the PHY is enabled Table 3: PHY 2 Power-Up Strap Options Strap Pin Pin# Wiring Value Setting/Note Function PHYAD0 COL 42 nc 1 PHYAD1 RXD_3 43 pull-up 1 PHYADDR=3 PHYAD2..4 RXD_2.._ nc 000 AN_EN LED_LINK 28 nc 1 Autoneg enable Note: LED must be wired to VCC AN1 LED_SPEED 27 nc 1 AN0 LED_ACT 26 nc 1 all modes CLK_OUT_EN GPIO1 21 pull-up 1 enable clock output FX_EN_Z RX_ER 41 nc 1 disable FX mode LED_CFG CRS 40 nc 1 mode1 MII_MODE RX_DV 39 pull-up 1 RMII Mode PCF_EN GPIO2 22 nc 0 RMII_MAS TXD_3 6 nc 0 enable RMII slave mode Note: only pins 43 and 6 are strapped differently from PHY1. 12

13 6 MDIO Management The PHYs can be configured for several modes of operation through the 2-wire MDIO/MDC management interface. Both PHY devices share the same mdio/mdc bus. The PHYs support an MDC clock of up to 25MHz. The PHYs support a so-called broadcast function when commands are sent to the PHY address 31, which then will be accepted by both PHYs at the same time. The PHYs can be individually addressed using the following MDIO addresses. Table 4: PHY MDIO Addresses MDIO Address PHY 1 Port 0 (Left RJ45 Connector, J5) 3 Port 1 (Right RJ45 Connector, J6) 31 Broadcast to both PHYs. Writes a register in both PHYs at the same time. Should be used for write commands only. 13

14 7 High Speed Mezzanine Card () Connector The connector used in applications is a custom version of the 0.5mm-pitch QTH-DP and mating QSH-DP series from Samtec, Inc. There are three banks in this connector. Bank 1 will have every third pin removed as is done in the QSH-DP/QTH-DP series. Bank 2 and Bank 3 have all of the pins populated as done in the QSH/QTH series. The default mating connector is the ASP The ASP connector can plug directly into hosts with QSH L-D-DP or QSH L-D connectors with the DP version having slightly better signal integrity. Figure 7: Samtec ASP Connector Pin out Table Table 4 shows for every pin of the connector on the board and the corresponding PHY signal. The signal suffix "_0" indicates PHY1 and "_1" indicates PHY2. Unused pins are left blank. Table 5: Connector Pin out Pin Function Bank No Function BANK Pin 14

15 MDIO MDC ref_clk_x1 rxclk_ intn_ txen_0 clk_out_ ,3 V 12 V txd[1]_0 rxcol_ txd[0]_0 rxcrs_ ,3 V 12 V rxerr_ rxdv_ ,3 V 12 V rxd[1]_ rxd[0]_ ,3 V 12 V txen_1 rxcol_ rxcrs_ ,3 V 12 V txd[1]_1 rxerr_ txd[0]_1 BANK 2 rxdv_ ,3 V 12 V rxd[1]_ reset_n rxd[0]_ ,3 V 12 V led_link_0 gpio4_ led_link_1 gpio4_ ,3 V 12 V gpio8_ gpio8_1 intn_ ,3 V 12 V clk_out_ ,3 V 12 V ,3 V 12 V ,3 V 12 V BANK ,3 V 12 V ,3 V 12 V

16 ,3 V 12 V ,3 V 12 V genio[0] ,3 V 12 V genio[3] genio[1] genio[4] genio[2] ,3 V 12 V otp[2] otp[0] otp[3] otp[1] ,3 V 12 V otpclk ,3 V PSNTn (gnd) 160 Notes: PSNTn is wired to GND on the daughter board (presence detect). Only the 3.3V power pins are used. The 12V pins are left unconnected. 16

17 7.2 Pin out description Dual DP83640 Ethernet PHY Daughter Board The following table describes the pin functions. The suffix _0/_1 corresponds to the PHY1/2 respectively. Table 6: Connector Pin out Description Function/Name Direction (at PHY) Description reset_n input Hardware reset when driven low (0). Must be 1 during normal operation. Use of the dedicated reset is not required as the power-on reset should be sufficient. Can be used as necessary. ref_clk_x1 input A 25MHz clock source. It is connected to the X1 input of PHY1 providing the reference clock source for the devices. MDIO Management mdc in Management clock input. The device supports up to 25MHz (standard is 2.5 MHz). Note: only one MDIO interface is available and all PHY devices communicate through this single interface using different MDIO addresses. mdio inout Management data input/output A 1.5K resistor to VCC is wired to it on the daughter board. RMII Parallel MAC Interface PHY 1 rxclk_0 out 50 MHz RMII reference clock from PHY 1 rxcol_0 out Receive collision indication from PHY. Used in half-duplex only. rxcrs_0 (crs_dv) out Receive carrier sense/data valid indication from PHY. rxd[1:0]_0 out RMII receive data. rxdv_0 out receive data valid from PHY 1 rxer_0 out receive error indication from PHY 1 txd[1:0]_0 in Transmit data to PHY 1. txen_0 in transmit enable to PHY 1 RMII Parallel MAC Interface PHY 2 rxcol_0 out Receive collision indication from PHY 2. Used in half-duplex only. 17

18 rxcrs_0 (crs_dv) out Receive carrier sense/data valid indication from PHY 2. rxd[1:0]_0 out RMII receive data rxdv_0 out receive data valid from PHY 2 rxer_0 out receive error indication from PHY 2 txd[1:0]_0 in transmit data to PHY 2 txen_0 in transmit enable to PHY 2 GPIO / 1588 gpio8 _0/1 in/out General Purpose I/O8 at PHY gpio4 _0/1 in/out General Purpose I/O4 at PHY Note this I/O is wired in parallel to the on-board 4x2 connector. clk_out_0 out Clock output (clk_out) from PHY 1. This is the 1588 synchronized reference clock (25MHz). clk_out_1 out Clock output (clk_out) from PHY 2. This is the 1588 synchronized reference clock (25MHz). Status / Interrupt led_link _0/1 out Active low indication when the link is operable. intn_0/1 out Interrupt (active low) from PHY. PSTNn -- pin wired to GND on the daughter board. Used as presence detect by the main board. Spare I/O genio[0,1,2,3,4] in/out General I/O available for arbitrary use. The pins are available on a 5x2 connector. PLCC-44 Socket I/O otp[0,1,2,3] in/out General I/O connected to the PLCC-44 connector for interfacing with an optional OTP device. otpclk in Clock input to OTP device. 18

19 8 PLCC-44 Socket The PLCC-44 Socket allows mounting of an optional OTP device for special purposes. The device has several I/O pins wired to the HMSC connector and operates with 3.3V power supplies. Figure 8: PLCC-44 Top View 19

20 Table 7: PLCC-44 Socket Pin Description Pin# Function Note Pin# Function Note 1 G* 23 G* 2 G* 24 G* 3 Vcc 3.3V supply 25 VCC 3.3V supply 4 G* 26 G* 5 G* 27 G* 6 G* 28 I/O to, otp[3] 7 G* 29 I/O to, otp[2] 8 G* 30 I/O to, otp[1] 9 G* 31 I/O to, otp[0] 10 GND 32 GND 11 G* 33 CLK to, otpclk 12 G* 34 G* 13 G* 35 VCC 3.3V supply 14 VCC 3.3V supply 36 G* 15 G* 37 G* 16 VCC 3.3V supply 38 G* 17 G* 39 G* 18 G* 40 G* 19 G* 41 G* 20 G* 42 G* 21 GND 43 GND 22 G* 44 G* Notes: VCC is 3.3V supply voltage GND is 0V supply ground. G* pins are connected to GND. These are unused I/O pins terminated to 0 to avoid floating signals. 20

21 9 Pin out for Altera Stratix II GX PCIe Board The following table shows the pin out for the -A and -B connectors available on the Stratix-II GX PCIe development board. Table 8: Interface Signals (Stratix II GX PCIe Board) A B Pin Function Bank No Function Pin B G4 AW AW3 G1 G5 AW AW4 G2 E4 AU AU1 E1 E5 AU AU2 E2 BANK A6 AN AN1 A3 A7 AN AN2 A4 C4 AR AR1 C1 C5 AR AR2 C2 F38 AD34 33 MDIO MDC 34 AG30 H36 35 FPGA_3V3_JTAG_TCK FPGA_3V3_JTAG_TMS HMSC_3V3_JTAG_TDO FPGA_3V3_JTAG_TDO 38 G22 AN22 39 ref_clk_x1 rxclk_0 40 W37 V37 D22 AR22 41 intn_0 42 AT22 F22 A22 AT21 43 txen_0 clk_out_0 44 AP22 B ,3 V 12 V 46 G33 AA33 47 txd[1]_0 rxcol_0 48 AE37 J39 G32 AB33 49 txd[0]_0 rxcrs_0 50 AE36 J ,3 V 12 V 52 J32 Y27 53 rxerr_0 54 AE39 K38 J31 AA26 55 rxdv_0 56 AE38 K ,3 V 12 V 58 K32 AA27 59 rxd[1]_0 60 AF39 L37 K31 AB27 61 rxd[0]_0 62 AG39 L ,3 V 12 V 64 K30 AD33 65 txen_1 rxcol_1 66 AG38 M37 L31 AE33 67 rxcrs_1 68 AG37 M ,3 V 12 V 70 M32 AB30 71 txd[1]_1 rxerr_1 72 AH39 N38 M31 AB29 73 txd[0]_1 rxdv_1 74 AH38 N ,3 V 12 V 76 N32 AB25 77 rxd[1]_1 78 AJ39 P37 N31 AC25 79 reset_n rxd[0]_1 80 AK39 P36 A 21

22 81 3,3 V 12 V 82 P30 AD26 83 led_link_0 gpio4_0 84 AK38 R35 R31 AD25 85 led_link_1 gpio4_1 86 AK37 R ,3 V 12 V 88 R30 AE27 89 gpio8_0 90 AN39 T38 T29 AE26 91 gpio8_1 intn_1 92 AM39 T ,3 V 12 V 94 W32(p) AM34 95 clk_out_1 96 W39 C39(p) Y31(n) AM W38 C38(n) 99 3,3 V 12 V 100 N27 Y AE35 U37 P28 Y AE34 U ,3 V 12 V 106 K34 AA AF37 N36 K33 AA AF36 N ,3 V 12 V 112 L34 AB AG36 K39 L33 AB AG35 L ,3 V 12 V 118 P27 AC AH37 R37 R27 AC AH36 R ,3 V 12 V 124 N34 AD AJ37 M39 N33 AD AJ36 M ,3 V 12 V 130 P34 AC AK36 N39 P33 AD BANK AK35 P ,3 V 12 V 136 R33 AB AL39 T35 R32 AC genio[0] 140 AL38 T ,3 V 12 V 142 T33 AD genio[3] genio[1] 144 AP39 R39 T32 AE genio[4] genio[2] 146 AP38 R ,3 V 12 V 148 U34 Y otp[2] otp[0] 150 AR39 U39 U33 AA otp[3] otp[1] 152 AT39 T ,3 V 12 V 154 T31(p) AE otpclk 156 AU39 V39(p) T30(n) AE AU38 V38(n) 159 3,3 V PSNTn (gnd)

23 10 Pin out for Altera Cyclone-III Starter Kit Board The following table shows the pin out for the connectors available on the Cyclone-III Starter Kit development board. IMPORTANT NOTE: The Cyclone-III Starter Kit Boards implements a 2.5V I/O interface to. Make sure to enable voltage overdrive on the Cyclone-III inputs to support the 3.3V input voltage for all pins coming from the PHY (see Quartus-II Device & Pin/ Pin Placement options setting) Table 9: Interface Signals (Cyclone-III Starter Kit Board) FPGA Pin Pin Function Bank No Function Pin FPGA Pin BANK E1 33 MDIO MDC 34 F3 35 FPGA_3V3_JTAG_TCK FPGA_3V3_JTAG_TMS HMSC_3V3_JTAG_TDO FPGA_3V3_JTAG_TDO 38 A1 39 ref_clk_x1 rxclk_0 40 A9 H6 41 intn_0 42 D3 M5 43 txen_0 clk_out_0 44 L6 45 3,3 V 12 V 46 T1 47 txd[1]_0 rxcol_0 48 M3 N7 49 txd[0]_0 rxcrs_0 50 T2 51 3,3 V 12 V 52 N8 53 rxerr_0 54 H15 J13 55 rxdv_0 56 H ,3 V 12 V 58 N10 59 rxd[1]_0 60 N16 N11 61 rxd[0]_0 62 N ,3 V 12 V 64 K17 65 txen_1 rxcol_1 66 R16 P11 67 rxcrs_1 68 T ,3 V 12 V 70 23

24 B2 71 txd[1]_1 rxerr_1 72 C2 B1 73 txd[0]_1 rxdv_1 74 C1 75 3,3 V 12 V 76 G2 77 rxd[1]_1 78 H2 G1 79 reset_n rxd[0]_1 80 H1 81 3,3 V 12 V 82 K2 83 led_link_0 gpio4_0 84 K5 K1 85 led_link_1 gpio4_1 86 L5 87 3,3 V 12 V 88 L2 89 gpio8_0 90 L4 L1 91 gpio8_1 intn_1 92 L3 93 3,3 V 12 V 94 D14 95 clk_out_1 96 F17 C F ,3 V 12 V 100 M P2 M P ,3 V 12 V 106 R T3 R R ,3 V 12 V 112 E G17 E G ,3 V 12 V 118 H K18 H L ,3 V 12 V 124 L L16 M M ,3 V 12 V 130 L L13 L M ,3 V 12 V 136 P R17 P genio[0] 140 R ,3 V 12 V 142 R5 143 genio[3] genio[1] 144 M6 R4 145 genio[4] genio[2] 146 N ,3 V 12 V 148 T otp[2] otp[0] 150 M13 T otp[3] otp[1] 152 N ,3 V 12 V 154 U otpclk 156 N17 V N ,3 V PSNTn (gnd)

25 11 References [1] DP83640 Precision PHYTER - IEEE 1588 Precision Time Protocol Transceiver, National Semiconductor 25

26 12 Contact MorethanIP GmbH info@morethanip.com Internet : Europe Muenchner Str. 199 D Karlsfeld Germany Tel : +49 (0) FAX : +49 (0) Nine Ways Research & Development Ltd Internet UK : pbates@nineways.co.uk : Unit G.15, idcentre, Lathkill House, rtc Business Park London Road, Derby. DE24 8UP United Kingdom Tel : +44 (0) FAX : +44 (0)