Microtronix ViClaro II Development Board

Transcription

1 Microtronix ViClaro II Development Board User Manual Woodcock St. London, ON Canada N5H 5S1

2 Document Revision History This user guide provides basic information about using the Microtronix ViClaro II Development Board. The following table shows the document revision history. Date Description December 2006 Initial Release Version 1.0 March 2006 Added Errata Version 1.1 How to Contact Microtronix Sales Information: Support Information: Website General Website: Nios Forum Website: Phone Numbers General: (001) Fax: (001) Typographic Conventions Path/Filename A path/filename [SOPC Builder]$ <cmd> A command that should be run from within the Cygwin Environment. Code Sample code. Indicates that there is no break between the current line and the next line. Page 2 of 13

3 Table of Contents Document Revision History... 2 How to Contact Microtronix Website... 2 Phone Numbers... 2 Typographic Conventions... 2 Introduction... 4 Power Supply... 5 Configuration... 5 Clocking... 5 Board Components User LEDs... 6 I 2 C... 6 DDR2 SDRAM... 7 HDMI Receiver... 8 HDMI Transmitter... 9 LVDS Expansion Headers Errata Appendix A. Schematics Page 3 of 13

4 Introduction The Microtronix ViClaro II Video Enhancement IP Development Platform is targetted at the development of consumer video display and imaging systems. It is designed to demonstrate the capabilities of Altera's for video and image enhancements applications in Video Display Controller ASSP systems. Figure 1 shows the ViClaro II board. Altera FPGA (EP2C35F484C6) 64 Mbyte DDR2 SDRAM (256 Mbit x 32) running up to 400 MHz data rate. Dual 5-channel LVDS receiver and LVDS transmitter HDMI receiver and analog video input HDMI transmitter I 2 C interface port Expansion header HDMI Receiver LVDS Receiver JTAG Expansion Headers Analog Video I 2 C HDMI Transmitter LVDS Transmitter DDR2 SDRAM POWER PLUG Page 4 of 13

5 Power Supply The on-board switching regulators generate all board voltages (1.2V, 1.8V, 2.5V and 3.3V). Additionally a linear regulator generates 5V required for the I 2 C and HDMI interfaces. The board is powered through the 2.5mm power jack input using an external +12V DC power supply. The center pin is the postive terminal. Configuration The device can be configured in JTAG stand-alone mode or active serial mode. At power-up the EPCS serial flash device configures the device. If the configuration is successful, the CONF_DONE LED illuminates. The EPCS device can be programmed using JTAG in-system programming. Clocking The board has a 50.0 MHz crystal oscillator. Figure 2 shows the clocking circuitry MHz Oscillator BUFFER Santa Cruz CLK12 (V12) CLK2 (M1) HDMI RX Audio Clock CLK0 (L1) HDMI RX Clock CLK1 (L2) Santa Cruz CLK3 (M2) LVDS RX Odd Clock LVDS RX Even Clock LVDSCLK5 (E12) LVDSCLK4 (A12) CLK13 (W12) (D5) PLL3_OUT Figure 2. Clocking Circuitry Page 5 of 13

6 Board Components The ViClaro II board is fitted with an Altera EP2C35 device in 484-pins Fineline BGA package with speedgrade -6. For more information on devices, refer to the Device Handbook. User LEDs There are two general purpose LEDs driven by the device. The LEDs are located in bank 1. Table 1. LED Pins LED1 LED2 R8 R7 I 2 C The ViClaro II board has an I 2 C interface, which can be used to access the (optional) I 2 C controller / slave in the. Also it provides access to the HDMI receiver and transmitter I 2 C interface. The interface has two level shifters, so an external I 2 C master can be connected without damaging the device. Also an 5 volt power supply and pull-up resistors are provided. Table 2. I2C Pins SCL SDA N2 N1 Page 6 of 13

7 DDR2 SDRAM The ViClaro II board has two Micron DDR2 SDRAM devices (MT47H16M16BG-3) with a total capacity of 256 Mbit x 32. The memory devices are connected to banks 5 and 6 of the device and uses the SSTL-18 I/O-standard. The two banks are powered with the 1.8V power supply. The board is designed for matched length traces across all DDR2 signals. All unused I/O-pins in the banks are connected to ground. Table x lists the DDR2 pin-outs. Table 3. DDR2 SDRAM Pins Cyclone II Pin Number Cyclone II Pin Number Cyclone II Pin Number Cyclone II Pin Number CKE H18 BA0 K18 DQ0 C22 DQ16 R19 CLK1 E18 BA1 K17 DQ1 F20 DQ17 Y20 CLK1# E19 A0 J19 DQ2 C21 DQ18 W20 CLK2 U18 A1 L17 DQ3 E20 DQ19 V19 CLK2# T18 A2 H19 DQ4 E21 DQ20 W22 CS# N22 A3 M16 DQ5 C20 DQ21 R17 RAS# P21 A4 K22 DQ6 E22 DQ22 W21 CAS# N21 A5 P19 DQ7 C19 DQ23 R18 WE# J18 A6 K21 DQ8 D22 DQ24 T22 ODT G18 A7 P20 DQ9 G21 DQ25 V21 A8 J22 DQ10 D21 DQ26 V22 A9 R21 DQ11 G22 DQ27 V20 DQS0 F22 A10 J15 DQ12 H21 DQ28 Y22 DQS0# F21 A11 J21 DQ13 J17 DQ29 U19 DQS1 L18 A12 R22 DQ14 H22 DQ30 Y21 DQS1# L19 DQ15 H16 DQ31 T21 DQS2 U22 DQM0 H17 DQS2# U21 DQM1 G17 DQS3 M18 DQM2 Y18 DQS3# M19 DQM3 Y19 Page 7 of 13

8 HDMI Receiver The Viclaro II board contains a dual analog / HDMI video receiver. The AD9880 from Analog Devices supports all HDTV formats (up to 1080p and 720 p) and display resolutions up to SXGA (1280 x 75 Hz). The HDMI receiver interface pins are located in bank 2 and this bank is powered at 3.3 volts. Table x lists the FPGA pins. Table. 4. HDMI Receiver Pins CLK L1 G6 H2 DE J3 G7 H1 HS J4 B0 D3 VS J5 B1 D4 FIELD J6 B2 E3 R0 F3 B3 E4 R1 F4 B4 C2 R2 G3 B5 C1 R3 G5 B6 D2 R4 H3 B7 D1 R5 H4 R6 J1 MCLK L2 R7 J2 SCLK L7 G0 E2 LRCLK L8 G1 E1 SPDIF D6 G2 F2 I2S0 M6 G3 F1 I2S1 H6 G4 G2 I2S2 G6 G5 G1 I2S3 H5 Page 8 of 13

9 HDMI Transmitter The ViClaro II board has a HDMI transmitter from Analog Devices. The AD9889B supports HDTV formats up to 1080p and computer graphics resolutions up to UXGA (1600 x 60 Hz). The HDMI transmitter interface pins are located in bank 1 and this bank is powered at 3.3 volts. Table 5. HDMI Transmitter Pins CLK Y3 MCLK R5 DE T3 SCLK W4 HS U3 LRCLK Y4 VS W3 SPDIF R6 D0 R1 I2S0 T5 D1 R2 I2S1 T6 D2 T1 I2S2 U4 D3 T2 I2S3 V4 D4 D5 D6 D7 D8 D9 D10 D11 U1 U2 V1 V2 W1 W2 Y1 Y2 Page 9 of 13

10 LVDS The ViClaro II board provides a dual LVDS transmitter running at 622 Mbps per channel and a dual LVDS receiver with each 5-channels running at 805 Mbps per channel. The LVDS receiver pins are located is bank 3 and 4 and are terminated with a 100 resistor. The LVDS transmitter pins are located in banks 7 and 8. All LVDS banks are powered at 2.5 volts. The LVDS connector is Hirose part number DF13-40DP-1.25V. The mating socket is DF13-40DS-1.25C For more information on the LVDS connectors see the Hirose website ( Table 6. LVDS pin numbers RXE_CLK+ A12 RXO_CLK+ E12 TXE_CLK+ AB9 TXO_CLK+ AB11 RXE_CLK- B12 RXO_CLK- D12 TXE_CLK- AA9 TXO_CLK- AA11 RXE_A+ A4 RXO_A+ A3 TXE_A+ AB3 TXO_A+ AB4 RXE_A- B4 RXO_A- B3 TXE_A- AA3 TXO_A- AA4 RXE_B+ A8 RXO_B+ A7 TXE_B+ AB7 TXO_B+ AB8 RXE_B- B8 RXO_B- B7 TXE_B- AA7 TXO_B- AA8 RXE_C+ A15 RXO_C+ A14 TXE_C+ AB14 TXO_C+ AB15 RXE_C- B15 RXO_C- B14 TXE_C- AA14 TXO_C- AA15 RXE_D+ A18 RXO_D+ A17 TXE_D+ AB17 TXO_D+ AB18 RXE_D- B18 RXO_D- B17 TXE_D- AA17 TXO_D- AA18 RXE_E+ A20 RXO_E+ A19 TXE_E+ AB19 TXO_E+ AB20 RXE_E- B20 RXO_E- B19 TXE_E- AA19 TXO_E- AA20 Page 10 of 13

11 Expansion Headers The ViClaro II board provides three expansion headers. These connectors use standard 0.1 headers and can be used for Altera daughter cards (e.g. Santa Cruz) or for debugging purposes. The expansion header signals are located in banks 1, 3, 4, 7, and 8. Due to the different bank power supplies, the expansion header signals located in banks 3, 4, 7, and 8 will drive out maximum 2.5 volts, while the signals in bank 1 will drive out 3.3 volts. All inputs are 3.3 volts complaint. If in a design both the LVDS signals and the expansion headers signals H11 and C14 are used, then the Quartus assignment Toggle Rate must set to 0 MHz to prevent a compilation error. Table 7. Expansion Header Pins GND 1 2 NC NC 1 2 GND J H14 C7 3 4 E7 H G11 C D7 F F10 C A10 B H7 C E15 F G7 D D15 M R16 AA W15 AB AA12 Y AB12 GND NC VIN 1 2 GND AA GND NC 3 4 GND AB GND 3.3V 5 6 GND T GND 3.3V 7 8 GND U P6 OSC 9 10 GND P GND NC GND P P3 M GND P NC 3.3V GND P N6 3.3V GND N N4 3.3V GND N GND Page 11 of 13

12 Errata An issue with the HDMI transmitter and receiver PLL power supply stability was identified. The effect of this issue may cause unstable behavior of the HDMI video data. To improve the stability an extra capacitor (range 2.2 uf 10 uf) must be added to the PLL power supply. Figure 3. HDMI Transmitter Figure 4. HDMI Receiver Page 12 of 13

13 Appendix A. Schematics Copyright 2006 Microtronix Datacom Ltd. All rights reserved. Altera and Nios II are Registered Trademarks of Altera Corporation. All other product or service names are the property of their respective holder. Page 13 of 13