FFSA TM. 130nm series

Transcription

1 130nm series

2 130nm series Toshiba Custom LSI Solution To ensure competitiveness in the marketplace, more sophisticated, more technology-intensive and higher-value-added products need to be created using a process of technological innovation. Toshiba s custom SoC solutions will give you an edge beyond your expectations. You can select a variety of solutions and services empowered by our experience and assets, to develop ASSPs for industrial, telecommunication, consumer, mobile, and amusement applications to support more value-added product development while reducing your development workload. Toshiba s ASIC (Application Specific IC) and FFSA (Fit Fast Structured Array) platforms help to deliver efficient solutions for custom SoC development to meet your business environment and requirements. Data compression Security Platform High Speed SerDes Design Consulting Storage Design Easy Prototyping TM ASIC Custom SoC Subsystem Metal Configurable Technology Package/PCB Design High Performance Technology Low Power Toshiba Custom LSI Solution

3 130nm series FFSA (Fit Fast Structured Array) FFSA devices use a silicon based master slice which is common to all customers in combination with upper metal layers which are reserved for customization. By customizing only a few masks FFSA offers much lower NRE costs than individual ASIC development. It also enables significant reductions in development costs and provides samples and mass-production in a shorter period of time than for conventional ASIC s. Additionally, FFSA enables higher performance and lower power consumption than (Field Programmable Gate Array) using ASIC design methodology and its library. FFSA is suitable for customers who are employing costly s to reduce initial investment, and for those who are aiming to differentiate their own products by customized SoCs. Customers spending a significant amount of NRE on ASIC development to obtain performance and lower power consumption which cannot be achieved with s will also benefit from an FFSA solution. Short time to market Low initial investment High performance (vs. ) Low power (vs. ) + 40 nm 28 nm 28 nm 20 nm 560 MHz 400 MHz 700 MHz SRAM max speed 1 GHz Power[W/MHz] 14.3 W 120 MHz 28nm 5X higher power efficiency 5.3 W 240 MHz 40nm Performance & power depend on design ASIC High performance Low power Chip size optimization Cost ROI Model ASIC Custom metal layers Pre-designed masterslice Customer logic Configuration of masterslice Memory macro Multiprotocol transceiver SerDes, DRAM PHY Multifunction I/O Biz Window ASIC Biz Window Qty features Random Logic Metal-Configurable Standard Cell Logic Blocks (CLB) SRAM Metal-Configurable 9 kbit Dual-Port SRAM Blocks (M9K) Individual Product Configuration With Only Four Metal Layers Integrated CPU Dual-Core Arm Cortex -A53 max MHz (1200 MHz) H/S Transceiver Multi-Protocol H/S Transceiver supporting up to 28 Gbps/Lane Mixed-Signal IP PLL, DLL, Temperature Sensor, E-Fuse OTP Memory Standard Cell Library and ASIC-like Design Methodology Common Base-Wafers (Masters) Shared Among Several Products High Performance Low Power Dissipation Small Die Size Structure Low NRE Short Design Time Short Lead Time H/S & Multi-Purpose I/O Metal-Configurable I/O Pad Cells in 16 Individual I/O Banks Individual Product Requires Only Four Metal-Layers

4 130nm series FFSA lineup By using ASIC development methodology and a cell library, FFSA is able to achieve high performance and low power consumption nearly equivalent to ASIC. By customizing metal layers FFSA is able to set the specifications of IP and IO embedded in the master slice. The 130nm process series joins the existing 28nm, 40nm, and 65nm process portfolio making FFSA a suitable option for the growing industrial equipment market. Feature 28 nm Fab : TSMC Transcelver speed : 28 Gbps DRAM speed : 2666 Mbps 40 nm Fab : GLOBALFOUNDRIES Transcelver speed : 12.5 Gbps DRAM speed : 1600 Mbps 65 nm Fab : GLOBALFOUNDRIES New! Transcelver speed : 6.5 Gbps DRAM speed : 1066 Mbps 130 nm Fab : Japan Semiconductor Corporation CY FFSA lineup

5 130nm series Process series specification Attribute Specification IP Specification Power supply voltage 3.3 / 1.5 (/ ) 1 port read/write SRAM 3.3 single power supply (embedded LDO)( / ) SRAM 1 port read/1 port write SRAM Junction temperature (Tj) 2 Package Type -40 to +125 QFP, BGA ROM 2 ports read/write SRAM 1port ROM Logic Gates to 912 K gates Output frequency : to 600MHz PLL Memory size 32 to 664 kbits (Optional:SSCG support) LDO single power supply version only Macro cell PLL 6 Reference CLK Output frequency 6 to 200 MHz to 600 MHz SRAM SRAM Type SRAM Macro Size 7 1 port read/write SRAM 1 port read/1 port write SRAM 2 ports read/write SRAM 8kbit bit/word(sram Macro) 7 2b x 4096w 4b x 2048w 8b x 1024w 16b x 512w I/O (GPIO, Oscillator cell) GPIO 3.3 mode Parameter IO Power supply voltage High-level input voltage Low-level input voltage Schmitt trigger hysteresis voltage High-level output voltage Low-level output voltage Symbol Condition min max Unit DDIO IH IL H IOH = -100 μa IOH = -2 ma DDIO- 3.6 DDIO OH IOH = -4 ma IOH = -8 ma IOH = -12 ma IOL = 100 μa IOL = 2 ma OL IOL = 4 ma IOL = 8 ma IOL = 12mA I/O (GPIO, Oscillator cell) GPIO 2.5 mode Parameter Symbol Condition min max Unit IO Power supply voltage High-level input voltage Low-level input voltage Schmitt trigger hysteresis voltage DDIO IH IL H IOH = -100 μa IOH = -1 ma DDIO IOH = -6 ma IOL = 100 μa IOL = 1 ma IOL = 6 ma High-level output voltage Low-level output voltage OH OL IOH = -2 ma IOL = 2 ma IOH = -4 ma IOL = 4 ma Oscillator cell Recommended Oscillator or Ceramic Resonator Frequency Range 10 to 30 MHz 1) GPIO 2.5 mode needs to supply 2.5 voltage externally. 2) Ambient temperature depends on usage conditions. 3) Regarding the number of usable gates, please consider the value as a guide as it varies depending on the customer s circuit. 4) 3.3 single-supply needs some restriction of core power supply and pin assignments of external capacitor to mount LDO. 5) External output capacitor is required. 6) Optional : Support spread spectrum clock generator (SSCG). 7) SRAM is provided combining above macro module to meet required bit / word configuration. External output capacitor is required. Please contact our sales for FFSA 65nm-28 series inquires.

6 130nm series Package Package requirements vary with each application system in which ASICs are incorporated. To satisfy all application needs, Toshiba offers a broad range of packaging options, based on small-form-factor and lightweight, low-profile, high-pin-count, high-speed and thermal dissipation technologies. 130nm series offers following package s lineup. Package lineup Type Pin Lead/Ball pitch Body size QFP 48 to , 0.5 mm 7x7 to 24x24 mm BGA 40 to to 1.0 mm 8x8 to 35x35 mm BGA pin number and body size are reference values. Applicable packages change depending on the master, the number of signals, etc. It is possible to make another packages suggestion to meet your specifications and business conditions. Please contact our sales for your package selection. Toshiba Custom SoC website For further information about this product, please visit: FFSA and Easy Prototyping TM are trademarks of Toshiba Electronic Devices and Storage Corporation. Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All other company names, product names, and service names may be trademarks of their respective companies.

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