µ-kernel Construction (12)

Transcription

1 µ-kernel Construction (12) Review 1

2 Threading Thread state must be saved/restored on thread switch We need a Thread Control Block (TCB) per thread TCBs must be kernel objects TCBs implement threads We need to find Any thread s TCB using its global ID The currently executing thread s TCB (per processor) At least partially. We have found some good reasons to implement parts of the TCB in user memory. 2

3 Thread Switch A B Thread A is running in user mode Thread A experiences an end-of-time-slice or is preempted by a (device) interrupt We enter kernel mode The microkernel saves the status of thread A on A s TCB The microkernel loads the status of thread B from B s TCB We leave kernel mode Thread B is running in user mode 3

4 Thread Switch A kernel B Processor IP SP FLAGS IP SP FLAGS tcb A user mode A 4

5 Thread Switch A kernel B? Processor IP SP FLAGS IP SP FLAGS tcb A IP SP FLAGS user mode A kernel 5

6 Thread Switch A kernel B Processor IP SP FLAGS Kernel code Kernel stack IP SP FLAGS tcb A IP SP FLAGS user mode A kernel 6

7 Thread Switch A kernel B Processor IP SP FLAGS Kernel code Kernel stack IP SP FLAGS tcb A IP SP FLAGS user mode A kernel 7

8 Thread Switch A kernel B Processor IP SP FLAGS Kernel code Kernel stack IP SP FLAGS tcb A user mode A kernel 8

9 Thread Switch A kernel B Processor IP SP FLAGS Kernel code IP SP FLAGS tcb A Kernel stack user mode A kernel 9

10 Thread Switch A kernel B Processor IP SP FLAGS Kernel code IP SP FLAGS tcb A Kernel stack user mode A kernel IP SP FLAGS tcb B Kernel stack 10

11 Thread Switch A kernel B Processor IP SP FLAGS Kernel code IP SP FLAGS tcb A Kernel stack user mode A kernel IP SP FLAGS tcb B Kernel stack 11

12 Thread ID TCB Direct Address movl thread_id, %eax movl %eax, %ebx andl mask_version, %eax shrl threadno_shift, %eax addl offset, %eax Kernel TCB area User %eax Thread TCB NopointerVersion Mask out lower bits Bitshift Add offset offset 12

13 0-Mapping Trick Direct Addressing Allocate physical memory for TCBs on demand Dependent on the max number of allocated TCBs Map all remaining TCBs to a 0-filled read-only page Any access to unused threads will result in invalid thread ID (0) Avoids additional check TCB Array (virtual memory) n m p q r Virtual TCB array requires 256 MB virtual memory for 256k potential TCBs 0 Physical Memory Frames containing TCBs. s 13

14 Basic Address-Space Layout 14

15 Address-Space Layout 32bits, Virtual TCBs User regions Shared system regions Per-space system regions Other kernel tables Physical memory Kernel code TCBs phys mem 15

16 Shared Region Synchronization We have Region shared among all address spaces Separate page table per address space Updates occur in dynamic region May lead to inconsistencies We need Some form of synchronization within dynamic region Make sure valid virtual memory mappings are synchronized phys mem Dynamic region Static region 16

17 TCB Area Synchronization Basic Algorithm Dedicate one table as master Synchronize with master table on page faults Page fault algorithm: if (master entry valid) { copy entry from master } else { create new entry in master copy entry from master } Master Table Dynamic region Static region 17

18 TCB Area Synchronization Modifying Mappings Page tables have multiple levels IA-32: page directories and page tables We only synchronize top level (page directory) Modifications in lower levels visible in all spaces Works even if entries are invalidated ptab ptab ptab 0 pdir pdir 18

19 IPC 19

20 IPC API Operations Message Types Send to Registers Receive from Strings Receive Map pages Call Send to & Receive any Send to & Receive from 20

21 Timeouts snd timeout, rcv timeout, xfer timeout snd, xfer timeout rcv time wait for send send message (xfer) wait for reply receive message (xfer) snd to min (xfer to snd, xfer to rcv) rcv to min (xfer to rcv, xfer to snd) (specified by the partner thread) 21

22 Timeouts relative timeout values 0 infinite 0 (16) 0(10) 0 1 (5) m(10) 0 e (5) 1 µs 610 h (log) 2 e m µs absolute timeout values 1 e (4) c m (10) 10 e clock = m (10) 0 clock + 2 (e+10) m (10) 22

23 Message Construction Messages are stored in registers (MR 0 MR 63 ) First register (MR 0 ) acts as message tag Subsequent registers contain Untyped words (u), and Typed words (t) (e.g., map item, string item) Number of untyped words Number of typed words Various IPC flags MR 0 label flags t uu Message Tag Freely available (e.g., request type) 23

24 Message Construction Typed items occupy one or more words Three currently defined items Map item (2 words) Grant item (2 words) String item (2+ words) Typed items can have arbitrary order MR 8 MR 7 MR 6 MR 5 MR 4 MR 3 MR 2 MR 1 3 MR 0 label String Item Map Item Message flags 5t uu 24

25 Map and Grant Items Two words Send base Fpage send base send fpage Map Item C MR i+1 MR i Lower bits of send base indicates map or grant item send base send fpage Grant Item C MR i+1 MR i location Fpage size 0wrx 25

26 String Items Up to 4 MB (per string) Compound strings supported Allows scatter-gather Incorporates cacheability hints Reduce cache pollution for long copy operations string pointer string length String Item MR i hhC MR i hh indicates cacheability hints for the string E.g., only use L2 cache, or do not use cache at all 26

27 Receiving Messages Receiver buffers are specified in registers (BR 0 BR 33 ) First BR (BR 0 ) contains Acceptor May specify receive window (if not nil-fpage) May indicate presence of receive strings/buffers (if s-bit set) receive window Acceptor 000s BR 0 27

28 What are Virtual Registers? Virtual registers are backed by either Physical registers, or Non-pageable memory UTCBs hold the memory backed registers UTCBs are thread local UTCB can not be paged No page faults Registers always accessible Preserved by switching UTCB on context switch Virtual Registers MR MR MR MR 4 MR 3 MR 2 MR 1 MR 0 Preserved by kernel during context switch UTCB MR 63 MR 62 MR 61 MR 4 MR 3 ESI EBX EBP Physical Registers 28

29 Implementation Goal Most frequent kernel op: short IPC Thousands of invocations per second Performance is critical Structure IPC for speed Structure entire kernel to support fast IPC What affects performance? Cache line misses TLB misses Memory references Pipe stalls and flushes Instruction scheduling 29

30 Requirements for Fast Path IPC Untyped message Single runnable thread after IPC Must be valid call-like IPC Send phase Target is already waiting Receive phase Sender is not ready to couple, causing up to block Switch threads, originator blocks No receive timeout Send timeout can be ignored: receiver is waiting Xfer timeouts do not apply for untyped messages 30

31 Memory is Forbidden Memory references are slow Avoid in IPC E.g., use lazy scheduling Avoid in common case E.g., (xfer) timeouts Microkernel should minimize artifacts Cache pollution TLB pollution Memory bus 31

32 TCB + kernel stack IPC EAX ECX EDX TSS.esp0 EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 32

33 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 33

34 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 34

35 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 35

36 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 36

37 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 37

38 IPC EAX ECX EDX EBX ESI EDI EBP ESP EFLAGS EIP CS SS DS ES FS GS 38

39 String IPC / memcpy Why? Trust Granularity Synchronous ( atomic ) transfer 39

40 Temporary Mapping 40

41 Temporary Mapping Select dest area (2x4 MB) 41

42 Temporary Mapping Select dest area (2x4 MB) Map into source AS (kernel) 42

43 Temporary Mapping Select dest area (2x4 MB) Map into source AS (kernel) Copy data 43

44 Temporary Mapping Select dest area (2x4 MB) Map into source AS (kernel) Copy data Switch to dest space 44

45 Temporary Mapping Copy page directory entry (PDE) from dest Addresses in temporary mapping area are resolved using dest s page table 45

46 Mapping 46

47 Mechanisms We need tools to build address spaces Map Unmap We need security Access permissions [rwx] We need resource control Use bits [accessed or dirty] Page fault messages [detect page use] 47

48 Map Map Map A B Agreed to receive mapping (BR 0 ). C Map D E 48

49 Unmap Unmap Unmap A B Implicit consent to unmap. C D E 49

50 Unmap Unmap Unmap A B Implicit consent to unmap. C D E 50

51 Grant Grant A B Grant C D E 51

52 Grant Grant A B Grant C D E 52

53 Access Rights Map r = Read w = Write x = execute A rwx rx B Mapper may restrict access rights Cannot extend its own access rights C rx rwx D rx 53

54 Access Rights Unmap r = Read w = Write x = execute A rwx B unmap(x) Mapper may revoke partial access rights Cannot extend other s access rights Unmap transitively affects mappings D C Preserves idea of synchronous mapping 54 rx rx

55 Mapping Regions A B C D 55

56 Mapping Regions: Flex Pages Abstraction: flex page Contiguous region of virtual address space Sparse physical mappings possible Called fpage Abstracts from architecture s page sizes Fpage semantics Inseparable object Aligned to its size Size is power of 2, min. 1024=2 10 byte 56

57 Fpage Encoding fpage( base, size=2 s ) s 10 base mod 2 s = 0 Special cases Complete address space (base=0, s=1) Nothing: nilpage (0) base / 2 10 s 0 r w x 22/54 bits 6 bits 4 bits 57

58 Status Bits Referenced, Written, executed Reset not visible here A B Query & reset Bitwise OR C D Reset not visible E here 58

59 Status Bits Referenced, Written, executed Query & reset Bitwise OR A B Reset not visible here C D E 59

60 Mapping Regions Implementation Based on page tables Physical page (frame) Basic mapping unit Determines minimum alignment Minimum fpage size Physical page size 60

61 Mapping Pages AS(A) map AS(B) Map pages by copying page table entries No support (yet) for Recursive unmap Combined status bits 61

62 Mapping Database physical frames physical frames AA A[1] BB B[7] DD CC D[0] C[2] E[0] XX EE 62

63 Page Fault IPC IP fault addr rwx Application PF IPC res IPC "PF" msg map msg Pager PF-IPC synthesized by the kernel, pager s reply caught by the kernel (application is not informed/involved) 63

64 IPC Map Configured by receiver receive window What about page faults? A Map item offset B 64

65 New Exception Handling Model IP SP EAX Application exception msg continue msg Exception Handler Except.-IPC synthesized by the kernel, handler s reply caught by the kernel (application is not informed/involved). IP SP EAX Kernel modifies register contents according to reply message 65

66 Other Key Ideas Avoid memory No indirection (TCB area) Lazy scheduling Make clever use of HW features Sysenter/sysexit Segmentation ( small spaces) Serialize recursive algorithms Recursive unmap 66