Dr. Ramesh K. Karne Department of Computer and Information Sciences, Towson University, Towson, MD /12/2014 Slide 1

Transcription

1 Dr. Ramesh K. Karne Department of Computer and Information Sciences, Towson University, Towson, MD /12/2014 Slide 1

2 Intel x86 Aseembly Language Assembly Language Assembly Language Programmer Processors and Co-processors Addressing Capability Why Assembly Code Assembly Language Development Env. Organization of Memory General Registers Addressing Schemes Stack Implementation Direct Addressing Indirect Addressing Index Addressing Base Addressing Addressing Code Segment Assembly Language Statements Programming 11/12/2014 Slide 2

3 Assembly Language An assemble reads a program in low level assembly language and generates an equivalent program in machine language Must understand instructions and basic architecture of the machine More details need to be coded in assembly You need to know about the processor (CPU) Each machine architecture has its own assembly langugage 11/12/2014 Slide 3

4 Assembly Language Programmer Need personality to learn details Able to understand reference manuals Develop solid understanding of how CPU and memory works Need good arithmetic skills; number representations and conversions Need to understand electronics 11/12/2014 Slide 4

5 Processors and Co-processors IBM Compatible PCs Use Intel x86 processors and math coprocessors 8080/ (77 instructions) (74 instructions) 387 (80 instructions) Pentium (1993) (80 instructions) 11/12/2014 Slide 5

6 Addressing Capability 16 bit real (DOS) 32 bit protected (Windows) 64 bit (64 bit addressing) 16 bit OS; 32 bit OS; 32/64 bit OS; 64 bit OS Programming language, compilers, linkers, debuggers, development environments all vary based on addressing capability of CPU 11/12/2014 Slide 6

7 Why Assembly Code? Need to understand real hardware Need to manipulate hardware at low levels Develop solid understanding of how CPU and memory works Need direct control over CPU Smaller programs at low level Have fun!!! 11/12/2014 Slide 7

8 Assembly Language Development Env Visual Studio environment (assembly calls from C/C++, or other languages) Limitations in using Visual Studio Batch files and self control environment Need an Editor for self control environment Use Bare Machine Development batch files to get full control of your program development and execution 11/12/2014 Slide 8

9 Organization of Memory Byte Word (2 bytes) Double Word (4 bytes) DW Quad Word (8 bytes) QW Paragraph (16 bytes) Memory is organized by bytes; they are numbered from 0 to n-1 11/12/2014 Slide 9

10 Organization of Memory Contd Bytes are stored in memory with addressing in sequence 0 to n-1 Bytes in words are stored in reverse order; 1234h is stored as 34h and 12h where 34h is stored in index 0 and 12h is stored in index 1 (Little Endian) Bits in a byte are stored in memory order Addressing has boundaries byte, word, doubleword, quadword and paragraph 11/12/2014 Slide 10

11 General Registers EAX (accumulator) primary register EBX (base register) ECX (count register) EDX (data register) ESI (source index) EDI (destination index) ESP (stack pointer) EBP (base pointer) 1 byte, 2 byte, 4 byte, 8 byte names for registers (al, ah; ax; eax, rax) 11/12/2014 Slide 11

12 General Registers Contd Flag Register (PSW) Status is indicated with individual bits: 0 - CF - Carry Flag 2 - PF - Parity Flag 4 - AF - Auxiliary carry Flag 6 - ZF - Zero Flag 7 - SF - Sign Flag 8 - TF - Trap Flag 9 - IF - Interrupt Flag 10 - DF - Direcetion Flag 11 - OF - Overflow Flag Flag bits are set by instructions Flag bits are basis of conditional jump instructions 11/12/2014 Slide 12

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15 Addressing Schemes Code Segment (CS) Data Segment (DS) Stack Segment (SS) Extra Segment (ES) used for data FS used for data GS used for data Segment registers contain segment address, offset contains offset address; memory is addressed by Segment:Offset; where Segment is the value in a given segment register and Offset is the address in the instruction. The address generation in 16 bit real mode, 32 bit protected mode and 64 bit addressing modes are calculated differently. 11/12/2014 Slide 15

16 Addressing Schemes Contd 16 bit real mode: 16 bit offset contained in the instruction added with a 4 bit segment register value resulting in 20 bit real address and 1MB memory 32 bit protected mode: 32 bit offset contained in the instruction added with a 4 bit selector value resulting in 32 bit virtual address and virtual memory 64 bit mode resulting in x64 address space (not too specific for now!) 11/12/2014 Slide 16

17 Stack Implementation PUSH and POP stack is managed as a segment with two special registers SS, ESP SS always contains the segment address of the stack; OS loads SS and it remains same for the program The ESP register contains an offset that points to the top of the stack At any time, the effective address (EA) of the top of the stack is formed from the contents of SS and ESP registers The stack is organized as 2 byte in 16 bit and 4 byte in 32 bit architectures The SS points to the lowest address in the list. The first push instruction places the data in the entry with the highest address. The next push instruction places data in the entry with the next highest address and so on. 11/12/2014 Slide 17

18 High Address 0x1000 Address 0x0ffc Address 0x0ff8 Stack Structure Data 1 Data 2 PUSH Data 2 PUSH Data 1 ESP Top of stack Low Address SS Bottom of stack

19 Direct Addressing To address memory, processor needs to know segment and offset address To specify a direct address, you specify the name of a segment register and an offset separated by a colon ex. DS:10ah data segment with offset 10ah a1 DD 0101h ; label DS:a1 when referencing data, if there is no segment specified, then it assumes DS 11/12/2014 Slide 19

20 Indirect Addressing Some times, you store the offset in a register then you can use indirect addressing using a register mov esi, 1000h mov eax, [esi] ;data at location esi is loaded into eax, uses DS implicitly mov edi, 1000h mov eax, [edi] ;data at location edi is loaded into eax, uses DS implicitly mov ebx, 1000h mov eax, [ebx] ;data at location ebx is loaded into eax, uses DS implicitly mov ebp, 1000h mov eax, [ebp] ; data at location ebp is loaded into eax, uses SS mov esp, 1000h mov eax, [esp] ; data at location esp is loaded into eax, uses SS 11/12/2014 Slide 20

21 Index Addressing indexing is needed to address arrays and lists indexing allows you to reference elements in an array with an index value 0, 1, 2, indexing allows you to reference items relative to the beginning of the array LIST DB 100 ;byte arrray i increments sequentially address the array by LIST + i where I can range from 0 to 99 BIGLIST DD 100 address the array by BIGLIST+i*4 ; 4 bytes increment 11/12/2014 Slide 21

22 Indexing Contd index value can also be stored in a register for use in calculating address the contents of the register can be changed to access different elements ESI and EDI registers are used as index registers BIGLIST DD 100 MOV ESI, 4 address the array by BIGLIST[ESI]; 4 bytes increment 11/12/2014 Slide 22

23 Base Addressing EBX is used as a base register for Data Segment DS EBP is used as a base register for Stack Segment SS indexing allows you to reference elements in an array with an index value 0, 1, 2, indexing allows you to reference items relative to the beginning of the array LIST DB 100 ;byte arrray i increments sequentially address the array by LIST + i where I can range from 0 to 99 BIGLIST DD 100 ; two dimensional array address the array by BIGLIST[EBX][EDI]; the contents of EBX and EDI are added to the offset of the data item 11/12/2014 Slide 23

24 The EBP Register Addressing of the stack is handled by ESP and SS Sometimes, you need to access stack at an arbitrary location You can use EBP register to hold the base address within the stack PUSH EBP MOV EBP, ESP MOV EAX, SS:[EBP+i] ; SS is implied by CPU as EBP is used as a base register ; now you can address inside stack as you wish POP EBP 11/12/2014 Slide 24

25 Addressing Code Segment Usually code segment is not modifiable Addressing of the code segment is automatically done by CPU with CS and EIP registers When a call instruction is executed, new CS and EIP are loaded A debugger may need CS and EIP values to check the instruction executed 11/12/2014 Slide 25

26 Assembly Language Statements each line can only contain one statement a statement may begin anywhere on the line upper or lower case letters are ok assembler makes it different in single or double quotes Hello, s comment starts with a semicolon three parts in an instruction and directives: name, opcode and operand, separated by a space; not all three are required in each instruction or a directive NEWSUM LABEL NEAR MOV EAX, TOTAL ADD EAX, SUBTOTAL PUSH EAX Names: 31 characters, letters digits _ $ Numbers: decimal, hex (h), binary(b) 11/12/2014 Slide 26

27 Assembly Language Program 11/12/2014 Slide 27