Extending the Power of FPGAs to Software Developers: The Journey has Begun Salil Raje Xilinx Corporate Vice President Software and IP Products Group Page 1
Agenda The Evolution of FPGAs and FPGA Programming IP-Centric Design with High Level Languages Software Defined Systems 2
The Evolution of FPGAs and FPGA Programming
The Evolution of Programmable Devices Logic Cells 1M 3D ICs 10K Programmable SoCs FPGAs 100 PLDs 1985 1995 2005 2015 2025 4
The Progression of FPGA Design Methodology Logic Cells 1M 10K Schematics RTL Programmable SoCs Software Defined IP-Centric with High-level Languages 3D ICs FPGAs 100 PLDs 1985 1995 2005 2015 2025 5
The Shift in Developer Personas Logic Cells 1M 10K Hardware Designer Schematics Hardware Designer Algorithm Developer Embedded SW Dev. RTL Programmable SoCs Application Developer Software Defined IP-Centric with High-level Languages 3D ICs FPGAs 100 PLDs 1985 1995 2005 2015 2025 6
IP-Centric Design with High Level Languages
Step 1: Leverage Broad Array of Hard and Soft IP + Embedded Processors Example of Hard IP: Zynq MPSOC Examples of Complex Soft IP AXI-MM AXI-Lite AXI-MM interconnect AXI-Lite interconnect AXI-MM AXI-MM AXI-Lite VDMA Deinterlacer V Scaler H Scaler CSC 422-444 420-422 420-422 Letterboxing AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S AXI4-S router 10x10 AXI4-S OTN Subsystem Video Subsystem HMC Controller Digital Pre-Distortion SmartConnect Page 8
Step 2: Develop New IP blocks in C/C++ Algorithmic Specification Micro-architecture Exploration RTL Implementation FPGA Integration Create IP from C/C++/System C algorithm specification Abstract algorithm verification 10,000x faster than RTL sim Traditional FPGA design experience not required Page 9
Step 3: Use Automated IP Assembly = IP Assembly Example: Zynq Processor Subsystem + Video Subsystem + 6 IP Blocks 4700 lines of VHDL (top-level connectivity only) Video Processing IP Subsystem
The Era of Software Defined Systems
Why FPGAs for Software Defined Systems? The Era of Virtualization Reconfigurable computing, storage and networking in the cloud The Thirst for Acceleration Heterogeneous computing Compute-intensive algorithms DNA sequencing Search engines Video processing Encryption/Decryption Packet routing FPGAs and Programmable SoCs: Power-efficient Reconfigurable Massively-Parallel Compute Engines Page 12
Query Example of FPGAs as Accelerators Smith-Waterman DNA Sequencing Application Reference Compares Query(N) with Reference(M) genome strings Involves MxN Matrix Computation and Dynamic Programming Maximal parallelism along diagonals Xilinx Virtex-7 690T (reference) Intel Xeon E5-2697 12 core Ratio Virtex-7 vs. Intel 12 core Intel Xeon Phi 5110P 60 core Ratio Virtex-7 vs. Intel 60 Core GCUPS 77.00 19.75 3.90 30.00 2.57 Watts 28.00 130.00 0.22 225.00 0.12 GCUPS/Watt 2.75 0.15 18.10 0.13 20.63 Page 13
Software Defined SoC Development C/C++ Development Standard Eclipse IDE Applications: Machine Vision Driver Assistance/ADAS Software-Defined Radio (SDR) Wireless Radio Surveillance UAV / Drones Full System Optimizing Compiler ARM Code Main( ) System-level Profiling Mark C/C++ Functions for Acceleration GCC Connectivity HLS+ SP&R Accelerator Func( ) Embedded ARM Processor Subsystem Programmable Logic Page 14
Software Defined Algorithm Acceleration in the Data Center Sample Applications: Machine Learning Bioinformatics Graph Processing Stringology Data Analytics Modelling Science Codes Signal Processing Video & Image Processing Software-Defined FPGA Acceleration Page 15
Software Defined Programmable Packet Processing High-level Specifications Moving to P4 industry standard Rapid Prototyping Compiler RTL output with verification testbench SP&R LogiCORE SmartCORE Custom Core SW Function SW & HW Implementation Deterministic Performance Optimal HW Implementation SDK/API Executable Image Search Co-Processor External Memory CPU 1GB 10GB 40GB FPGA or Programmable SoC 100GB Softly Defined Packet Processor Page 16
Platforms Enable Software Defined FPGA Systems Pre-defined Platform Hardware System Performance Partial Board Design Algorithms Support & Host Reconfig Analysis Software Stack Page 17
Summary We re making major investments in next generation silicon and tools that will revolutionize FPGA design HW designers: SW developers: C-based IP development + high-level IP assembly are the next step beyond RTL Software-defined algorithm development + platforms will enable you to exploit the power of FPGAs & SoCs Page 18
Xilinx Wants You: Researchers, Academics Xilinx University Program: Early Access Program Full license available in donation program Academic price on Alpha Data boards Visit www.xilinx.com/university Page 19
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