CN310 Microprocessor Systems Design Micro Architecture Nawin Somyat Department of Electrical and Computer Engineering Thammasat University 28 August 2018
Outline Course Contents 1 Introduction 2 Simple Computer 3 Micro Architecture 4 Peripherals 5 Applications Outline 1 Diagram 2 Architecture Processor Core Memory Buses 3 Instruction Set Basics Data Access Control Flow CN310 Microprocessor Systems Design 2 / 60
Block Diagram A graphical representation of principal structure and its interconnections, used for a higher level, less detailed description of the overall concepts. Blocks: parts / components / functions Lines: connections / relationships Thick lines: grouped connections Arrows: direction of energy / current / signal / data CN310 Microprocessor Systems Design 3 / 60
Block Diagram CN310 Microprocessor Systems Design 4 / 60
Block Diagram CN310 Microprocessor Systems Design 5 / 60
Schematic A graphical representation of the elements of a system using abstract, graphic symbols rather than realistic pictures. CN310 Microprocessor Systems Design 6 / 60
Timing Diagram A graphical representation of the time variation of signals, as well as the timed relationship between the signals. CN310 Microprocessor Systems Design 7 / 60
What is Microprocessor A device incorporates most or all of the functions of a central processing unit (CPU) on a single integrated circuit. CN310 Microprocessor Systems Design 8 / 60
What is Microprocessor An electronic component: Need fixed supply DC voltage (Vcc) and ground (GND). Operations rely on voltage signal. Internal operations are based on transistors. A digital IC: Operate with respect to clock signal. Interpret voltage level as logic. A device with constrained electrical properties: Can supply only limited current (sink > source) When interfacing with analog signal, input voltage must not exceed supply voltage. A device with processing capability: compared with similar processor core More frequency (MHz) means faster computation. Larger data width (8bit < 16bit < 32bit < 64bit) means more data processing and transfer capability. CN310 Microprocessor Systems Design 9 / 60
Cautions Microprocessor is built using CMOS technology Lower supply voltage (3.3V,2.5V,1.8V) uses less power, but will be damaged from 5V circuit. Power loss is proportional to switching frequency. Vulnerable to electrostatic discharge (ESD). Microprocessor executes code within memory. Memory address must be aligned with instruction/data width. Microprocessor selection may need to concern regulations. Thermal properties: operating temperature, heat dissipation. Electromagnetic properties: EMC. Production requirements: lead-free, RoHS. CN310 Microprocessor Systems Design 10 / 60
Processor Core A microprocessor is a programmable chip that is used for executing instructions to process data or control other devices. CN310 Microprocessor Systems Design 11 / 60
Processor Core Control Unit: manage sequence of processing, e.g. Fetch and execute instructions. Move data among memory locations. Branch to separate instruction based on decisions. Arithematic and Logic Unit: perform mathematical and logical operations, e.g. Addition, subtraction, multiplication, and division AND, OR, XOR, and shift operations. Registers and Flags: Instruction register/decoder: Program counter (PC): memory address of next instruction Memory bus: path to access memory CN310 Microprocessor Systems Design 12 / 60
Processor Core: Example CN310 Microprocessor Systems Design 13 / 60
Processor Core: Example ARM CN310 Microprocessor Systems Design 14 / 60
Processor Core: Example AVR CN310 Microprocessor Systems Design 15 / 60
Processor Core: Example Core 2 CN310 Microprocessor Systems Design 16 / 60
Concepts Instruction = what to do! Register = temporary memory Data = intermediate (constant) or reference (register/memory) Memory = place of code (ROM) or data (RAM) Address = location in memory of code/data CN310 Microprocessor Systems Design 17 / 60
Architecture Fundamental operational structure of processor core from programming viewpoint Instruction set Registers Data types Addressing modes Memory architecture Interrupt and exception handling External I/O CN310 Microprocessor Systems Design 18 / 60
Instruction Set An instruction set is a list of all the opcodes (machine language) that a processor can execute. instruction = opcode + operands CN310 Microprocessor Systems Design 19 / 60
Instruction Set Registers for arithmetic, addressing, or control functions Memory locations or offsets Operands referred by addressing modes Arithmetic instructions, e.g. add, subtract Logic instructions, e.g. and, or, not Data instructions, e.g. move, input, output, load, store Control flow instructions, e.g. goto, if-goto, call, return Special instructions, e.g. test-and-set, vector/floating-point CN310 Microprocessor Systems Design 20 / 60
Instruction set Other than their functions, instructions may be grouped based on the number of operands. 0-operand (stack machines): arithmetic operations use data from stack. push a; push b; add; pop c; 1-operand (accumulator machines): specify an operand (register, mem location, constant) with implicit accumulator load a; add b; store c; 2-operand: load a,reg1; load b,reg2; add reg1,reg2; 3-operand: complex operations or addressing modes CISC = move a,reg1; add reg1,b,c; RISC = load a,reg1; add reg1,reg2,reg3; (add reg1+reg2 -> reg3) more operands: CN310 Microprocessor Systems Design 21 / 60
Registers and Flags Registers are limited internal storage within microprocessor, fastest to access from MPU side. Used as temporary storage for execution input and output Indicate the execution capability of instruction/data, e.g. 8bit, 16bit, 32bit, 64bit Reflect the size of word, group of bits that processor can handle in one operation Flags refer to one or more bits within a register, that store a binary value representing a specific meaning CN310 Microprocessor Systems Design 22 / 60
Registers and Flags Instruction registers stores the instruction currently being executed or decoded General purpose registers hold data/address values Data registers hold numeric values Address registers hold index values for memory addressing Control and status registers include program counter, stack pointer, and status register Conditional registers hold enable/disable conditions for specific instructions Special purpose registers store program state Hardware registers contain bits of hardware state. Some architectures include additional registers, e.g. floating point registers, vector registers CN310 Microprocessor Systems Design 23 / 60
AVR Registers AVR architecture uses fast-access register file containing 32 x 8-bit registers. Single clock cycle access time Sixteen 16-bit addressable units CN310 Microprocessor Systems Design 24 / 60
AVR Status Register Status Register (SREG) is updated after all arithmetic and logical instructions, containing a set of status flags: I: Global Interrupt Enable H: Half Carry Flag V: Twos Complement Overflow Flag Z: Zero Flag T: Bit Copy Storage S: Sign Bit N: Negative Flag C: Carry Flag CN310 Microprocessor Systems Design 25 / 60
Memory Models Memory model is the way that processor can reference to an entity in memory. Flat memory model: single space up to 2 n Simple, efficient for single task. Not appropriate for multitasking OS (required MMU) Paged memory model: multiple pages, each page up to 2 n Suitable for multitasking environment Harder for low-level management Segmented memory model: combined segment:offset More efficient due to variable page boundaries More difficult for compilers CN310 Microprocessor Systems Design 26 / 60
Memory Map A memory map is a representation of memory layout for storing code and data. Program code Internal or external flash memory Read/write memory Internal or external RAM Hardware registers mapping CN310 Microprocessor Systems Design 27 / 60
Harvard Architecture Harvard code and data use separate memory space. CN310 Microprocessor Systems Design 28 / 60
von Neumann Architecture von Neumann code and data use shared memory space. CN310 Microprocessor Systems Design 29 / 60
Cache Memory CPU cache is a smaller, faster memory used by CPU to reduce the average time to access system memory. Cache stores copies of frequently used code/data in main memory Modern processors integrate three types of cache Instruction cache to speed up executable instruction fetch. Data cache to speed up data fetch and store. Translation lookaside buffer to speed up virtual-to-physical address translation Efficiency depends on hit/miss ratio CN310 Microprocessor Systems Design 30 / 60
Architecture Classification Instruction Set: Complex Instuction Set Computer (CISC): limited accumulators, complex instruction set, various addressing modes. Aim for 1 processing/1 instruction = small code size Reduced Instruction Set Computer (RISC): general-purpose registers, simple instruction set, limited addressing modes, load-store execution Aim for 1 clock/1 instruction = better MIPS Others: DSP, VLIW,... Word size: 8 / 16 / 32 / 64 bit Memory space: program and data. von Neumann architecture: share address space. Harvard architecture: separate address space. CN310 Microprocessor Systems Design 31 / 60
Questions What architecture types of AVR core How many registers in AVR core What is word length of AVR core How large memory can be addressed How many addressing modes AVR core support CN310 Microprocessor Systems Design 32 / 60
Processor Bus Processor bus is a subsystem that transfers data between components inside a microprocessor. Data bus: transport data to/from memory Address bus: provide address of memory locations Control bus: control devices on bus There are different type of processor buses System bus or memory bus: CPU main memory Peripheral bus or I/O bus: bridge peripheral devices CN310 Microprocessor Systems Design 33 / 60
Bus Addressing & Timing Processor core accesses to code and data in memory using a sequence of signals from address/data/control buses. Generate and hold address value on address bus Some address bits may be used for memory chip selection Assert Read/Write signal from control bus Access data via data bus CN310 Microprocessor Systems Design 34 / 60
System and Peripheral Clocks Microprocessor components are digital logics which operate w.r.t. clock signals. Clock source may be external or internal oscillator PLL (phase-locked-loop) multiplies clock frequency Use low-frequency oscillator Prescalar divides clock frequency Peripheral devices Lower-speed devices CN310 Microprocessor Systems Design 35 / 60
System and Peripheral Clocks: Example AVR CN310 Microprocessor Systems Design 36 / 60
System and Peripheral Clocks Clock source can be selected via I/O register Changing clock source requires time to stabilize frequency Adjusting clock frequency makes trade-off between processing power and power consumption CN310 Microprocessor Systems Design 37 / 60
Computer Buses Computer buses cover data pathway among CPU, mainboard chipset, and external devices. Northbridge or memory controller hub: front-side bus Memory (RAM) Highspeed graphics subsystem Southbridge or I/O controller hub: PCI bus = standardized bus for expansion cards SATA and IDE = hard disk drive SPI bus = flash BIOS, SMBus = battery USB bus CN310 Microprocessor Systems Design 38 / 60
Computer Buses: Example CN310 Microprocessor Systems Design 39 / 60
Instruction Set An instruction set is a list of all the opcodes (machine language) that a processor can execute. Arithmetic instructions, e.g. add, subtract Logic instructions, e.g. and, or, not Data instructions, e.g. move, input, output, load, store Control flow instructions, e.g. goto, if-goto, call, return Special instructions, e.g. test-and-set, vector/floating-point Programming env. at level of machine instructions includes Data types Addressing mode Execution status Instruction timing CN310 Microprocessor Systems Design 40 / 60
Instruction Cycle Fetch-and-Execute cycle is a sequence where instructions are fetched from memory, then executed. 1 Fetch the instruction at PC into instruction register: IR [PC] 2 Decode the instruction and increment PC: PC PC + n 3 Fetch operands from memory (instruction with indirect address) 4 Execute the instruction by control unit or ALU 5 Store result to memory CN310 Microprocessor Systems Design 41 / 60
Execution Timing The Parallel Instruction Fetches and Instruction Executions Single Cycle ALU Operation CN310 Microprocessor Systems Design 42 / 60
Accumulator Architecture CISC processors have limited accumulators, complex instructions, orthogonal addressing modes. Load data into accumulator. Execute instructions with additional data from memory. Store results into memory. CN310 Microprocessor Systems Design 43 / 60
RISC Architecture RISC processors have many working registers, simple addressing modes, memory access via load/store instructions. Load data from memory into registers Execute instructions using registers Store results into memory CN310 Microprocessor Systems Design 44 / 60
ALU-Related Instructions Basic arithematic and logic instructions that almost ALUs can perform: Integer arithmetic operations: addition, subtraction, multiplication, division Bitwise logic operations: AND, NOT, OR, XOR Bit-shifting operations: to the left or right, with or without sign extension Shifts can be interpreted as multiplications by 2 and divisions by 2. Additional complex ALU operations are optional for the design of instruction set architecture. Floating-point calculation is handled by FPU, not ALU. CN310 Microprocessor Systems Design 45 / 60
Binary Representation Two s complement of a binary number is the value obtained by subtracting the number from 2 n. 1 = 2 8 (100000000) 1(00000001) = 11111111 Encode negative numbers into ordinary binary without special circuit to handle signed computation Represent number in the range 2 n 1 to +2 n 1 1 binary base-10 binary base-10 0111 1111 127 1111 1111-1 0111 1110 126 1111 1110-2 0000 0001 1 1000 0001-127 0000 0000 0 1000 0000-128 CN310 Microprocessor Systems Design 46 / 60
Machine Data Size Processor core view machine data types according to the relationship between instructions and registers/flags. Bit: 0 or 1 Each flag in conditional registers can be accessed via specific instructions A few processor cores can access general purpose registers at bit level Byte: an octet (8-bit) Similar to word for 8-bit processors Need downsizing for 16-/32-/64-bit processors Word: word length equals the size of registers Some processors support instructions that handle operands with 2 words or more CN310 Microprocessor Systems Design 47 / 60
Machine Data Types Programming data types are translated at compiler level into machine data types Boolean, char, integer types are treated as word-length data Floating-point value is handled by software or co-processor Integer processing is the fastest since it is word-aligned Floating-point processing is the slowest if no co-processor Arithematic operations based on native instructions, e.g. add, shift, are faster In C language, integer promotion rules are applied for the computation of char/integer/long data CN310 Microprocessor Systems Design 48 / 60
Status Register Status register refers to a group of registers containing flags (bits) showing the status of microprocessor and execution result. Typical statuses include: Carry Flag = result has carry from arithemetic operation Zero Flag = result is zero Negative Flag = result is negative Overflow Flag = result is overflow Parity Flag = result is odd or even Interrupt Enable Flag = flag to enable/disable interrupt Trap Flag = trap condition occurs w.r.t. execution result Some instructions can manipulate these flags directly, or execute according to their value. CN310 Microprocessor Systems Design 49 / 60
Data Instructions The movement of data between processor and external devices is handled via the control unit through processor bus. Set register to a constant value. Move data among registers and memory locations: copy, move, load, store. Read and write data with hardware devices: in, out. Flexibility of referencing memory locations allow processor to handle data transfer easier addressing mode. CN310 Microprocessor Systems Design 50 / 60
Addressing Modes Addressing mode specifies how to calculate the effective memory address of an operand by using information held in registers and/or constants. Register: operand is in the register Immediate: operand is in the instruction itself Direct: address of operand is in the instruction Register Direct: address of operand is in the given register Base Displacement: address is the sum of register content and a constant Indirect: instruction have address, the contents at the address is the address of the operand Register Indirect: register contains address, the contents at the address is the address of the operand CN310 Microprocessor Systems Design 51 / 60
Addressing Modes Addressing modes for code Direct: jump addr Register Direct: jump reg Base Displacement: jump offset Addressing modes for data Direct: load reg,addr Base Displacement: load reg,base,offset CN310 Microprocessor Systems Design 52 / 60
Addressing Modes: Examples Direct Data Addressing CN310 Microprocessor Systems Design 53 / 60
Addressing Modes: Examples Indirect Data Addressing with Displacement CN310 Microprocessor Systems Design 54 / 60
Control Flow Instructions Jumping (unconditional) or Branching (conditional) is the ability to load the PC register with a new address that is not the next sequential address. executing these instructions alters the flow of software. Jump instructions: Absolute: local or long Relative Subroutine instructions: Call and return Software traps Branch instructions: Status register s flags Comparison result CN310 Microprocessor Systems Design 55 / 60
Control Flow Instructions: Branch Instructions CN310 Microprocessor Systems Design 56 / 60
Subroutine Call A subroutine is a group of instructions that will be used repeatedly in different locations of the program. basis of function call in high-level language. CALL instruction: redirect the execution to the subroutine RET insutruction: return the execution to the calling routine To return after subroutine ends, how processor can remember its code address and execution state. CN310 Microprocessor Systems Design 57 / 60
Stack Processor stack is a memory portion used as temporary storage during execution. Stack operation is based on last-in, first-out mechanism Push register into stack Pop top stack to register Stack is always used for saving status and passing arguments PC, status registers, working registers PC, calling arguments Return value CN310 Microprocessor Systems Design 58 / 60
Stack: Frame Stack pointer (SP) is the memory address of stack last data Kept by stack pointer register Either increase or decrease, depend on processor Stack overflow is the problem of pushing too much data into stack CN310 Microprocessor Systems Design 59 / 60
Stack: Subroutine Hardware level: PC and SREG are saved by default. Software level: required registers by PUSH instruction. High-level language: all registers before each function call. CN310 Microprocessor Systems Design 60 / 60