Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Low-Voltage and Standard-Voltage Operation 5. (V CC = 4.5V to 5.5V).7 (V CC =.7V to 5.5V) 1.8 (V CC = 1.8V to 3.6V).1 MHz Clock Rate (5V) Compatibility 8-Byte Page Mode Block Write Protection Protect 1/4, 1/, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for Both Hardware and Software Data Protection Self-Timed Write Cycle (1 ms max) High Reliability Endurance: 1 Million Write Cycles Data Retention: 1 Years ESD Protection: >4V Automotive Grade and Extended Temperature Devices Available 8-Pin PDIP and JEDEC SOIC Packages Description The AT51//4 provides 14/48/496 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 18/56/51 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low power and low voltage operation are essential. The AT51//4 is available in space saving 8-pin PDIP and 8-pin JEDEC (SOIC) packages. The AT51//4 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface coisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable itructio are provided for additional data protection. Hardware data protection is provided via the WP pin to protect agait inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Pin Configuratio Pin Name Function 8-Pin PDIP SPI Serial EEPROMs 1K (18 x 8) K (56 x 8) 4K (51 x 8) AT51 AT5 AT54 SPI, 1K Serial E PROM CS SCK SI Chip Select Serial Data Clock Serial Data Input CS SO WP GND 1 3 4 8 7 6 5 VCC HOLD SCK SI SO Serial Data Output GND VCC Ground Power Supply 8-Pin SOIC WP HOLD Write Protect Suspends Serial Input CS SO WP GND 1 3 4 8 7 6 5 VCC HOLD SCK SI Rev. 66E 8/98 1
Absolute Maximum Ratings* Operating Temperature... -55 C to + 15 C Storage Temperature... -65 C to + 15 C Voltage on Any Pin with Respect to Ground...-1.V to + 7.V Maximum Operating Voltage... 6.5V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. DC Output Current... 5. ma Block Diagram AT51//4
AT51//4 Pin Capacitance (1) Applicable over recommended operating range from T A = 5 C, f = 1. MHz, V CC = +5.V (unless otherwise noted). Symbol Test Conditio Max Units Conditio C OUT Output Capacitance (SO) 8 pf V OUT = V C IN Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pf V IN = V Note: 1. This parameter is characterized and is not 1% tested. DC Characteristics Applicable over recommended operating range from: T AI = -4 C to +85 C, V CC = +1.8V to +5.5V, T AC = C to +7 C, V CC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Max Units V CC1 (1) Supply Voltage 1.8 5.5 V V CC Supply Voltage.7 5.5 V V CC3 Supply Voltage 4.5 5.5 V I CC1 Supply Current V CC = 5.V at 1 MHz, SO = Open 3. ma I CC Supply Current V CC = 5.V at MHz, SO = Open 6. ma I SB1 (1) Standby Current V CC = 1.8V CS = V CC 1 µa I SB Standby Current V CC =.7V CS = V CC 1 µa I SB3 Standby Current V CC = 5.V CS = V CC 1 µa I IL Input Leakage V IN = V to V CC -.6 3. µa I OL Output Leakage V IN = V to V CC, T AC = C to 7 C -.6 3. µa V IL () Input Low Voltage -.6 V CC x.3 V V IH () Input High Voltage V CC x.7 V CC +.5 V V OL1 Output Low Voltage I OL =. ma.4 V 4.5V V CC 5.5V V OH1 Output High Voltage I OH = -1. ma V CC -.8 V V OL Output Low Voltage I OL =.15 ma. V 1.8V V CC 3.6V V OH Output High Voltage I OH = -1 µa V CC -. V Notes: 1. This parameter is preliminary and Atmel may change the specificatio upon further characterization.. V IL min and V IH max are reference only and are not tested. 3
AC Characteristics Applicable over recommended operating range from T A = -4 C to +85 C, V CC = As Specified, CL = 1 TTL Gate and 1 pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units f SCK SCK Clock Frequency.1.1.5 MHz t RI Input Rise Time µs t FI Input Fall Time µs t WH SCK High Time 8 t WL SCK Low Time 8 t CS CS High Time 5 5 1 t CSS CS Setup Time 5 5 1 t CSH CS Hold Time 5 5 1 t SU Data In Setup Time 5 5 1 t H Data In Hold Time 5 1 1 t HD Hold Setup Time 1 1 4 t CD Hold Hold Time 4 t V Output Valid 4 8 t HO Output Hold Time 4 AT51//4
AT51//4 AC Characteristics (Continued) Applicable over recommended operating range from T A = -4 C to +85 C, V CC = As Specified, CL = 1 TTL Gate and 1 pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units t LZ Hold to Output Low Z 1 1 1 t HZ Hold to Output High Z 1 1 1 t DIS Output Disable Time 5 5 1 t WC Write Cycle Time 1 ms Endurance 5.V, 5 C, Page Mode 1M Write Cycles Note: 1. This parameter is characterized and is not 1% tested. 5
Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT51//4 always operates as a slave. TRANSMITTER/RECEIVER: The AT51//4 has separate pi designated for data tramission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contai the op-code that defines the operatio to be performed. The op-code also contai address bit A8 in both the READ and WRITE itructio. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT51//4, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT51//4 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT51//4. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low, all write operatio are inhibited. WP going low while CS is still low will interrupt a write to the AT51//4. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation. SPI Serial Interface 6 AT51//4
AT51//4 Functional Description The AT51//4 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 685 and 68HC11 series of microcontrollers. The AT51//4 utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Table 1. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low CS traition. Table 1. Itruction Set for the AT51//4 Itruction Name Itruction Format Operation WREN X11 Set Write Enable Latch WRDI X1 Reset Write Enable Latch RDSR X11 Read Status Register WRSR X1 Write Status Register READ A11 Read Data from Memory Array WRITE A1 Write Data to Memory Array Note: A represents MSB address bit A8. WRITE ENABLE (WREN): The device will power up in the write disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. The WP pin must be held high during a WREN itruction. WRITE DISABLE (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register itruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Bit 1 Bit X X X X BP1 BP WEN RDY Table 3. Read Status Register Bit Definition Bit Bit (RDY) Bit 1 (WEN) Definition Bit (BP) See Table 4. Bit 3 (BP1) See Table 4. Bit = (RDY) indicates the device is READY. Bit = 1 indicates the write cycle is in progress. Bit 1 = indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bits 4-7 are s when device is not in an internal write cycle. Bits -7 are 1s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The AT51//4 is divided into four array segments. Top quarter (1/4), Top half (1/), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The two bits, BP1 and BP are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g. WREN, t WC, RDSR). Table 4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP AT51 AT5 AT54 None None None 1 (1/4) 1 6-7F C-FF 18-1FF (1/) 1 4-7F 8-FF 1-1FF 3 (All) 1 1-7F -FF -1FF READ SEQUENCE (READ): Reading the AT51//4 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code (including A8) is tramitted via the SI line followed by the byte address to be read (A7-A). Upon completion, any data on the SI line will be ignored. The data (D7-D) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. 7
WRITE SEQUENCE (WRITE): In order to program the AT51//4, the Write Protect pin (WP) must be held high and two separate itructio must be executed. First, the device must be write enabled via the Write Enable (WREN) Itruction. Then a Write (WRITE) Itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR itruction. A Write Itruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code (including A8) is tramitted via the SI line followed by the byte address (A7-A) and the data (D7-D) to be programmed. Programming will start after the CS pin is brought high. (The LOW to High traition of the CS pin must occur during the SCK low time immediately after clocking in the D (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Itruction. If Bit = 1, the WRITE cycle is still in progress. If Bit =, the WRITE cycle has ended. Only the READ STATUS REGISTER itruction is enabled during the WRITE programming cycle. The AT51//4 is capable of an 8-byte PAGE WRITE operation. After each byte of data is received, the three low order address bits are internally incremented by one; the six high order bits of the address will remain cotant. If more than 8 bytes of data are tramitted, the address counter will roll over and the previously written data will be overwritten. The AT51//4 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the WP pin is brought low or if the device is not Write enabled (WREN), the device will ignore the Write itruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. 8 AT51//4
AT51//4 Timing Diagrams Synchronous Data Timing (for mode ) t CS CS V IH V IL tcss t CSH SCK V IH t WH t WL V IL t SU t H SI V IH V IL VALID IN t V t HO t DIS SO V OH HI-Z HI-Z V OL WREN Timing WRDI Timing 9
RDSR Timing CS SCK 1 3 4 5 6 7 8 9 1 11 1 13 14 SI INSTRUCTION DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 1 MSB WRSR Timing CS SCK 1 3 4 5 6 7 8 9 1 11 1 13 14 15 SI INSTRUCTION DATA IN 7 6 5 4 3 1 SO HIGH IMPEDANCE READ Timing 1 AT51//4
AT51//4 WRITE Timing CS SCK 1 3 4 5 6 7 8 9 1 11 1 13 14 15 16 17 18 19 1 3 SI INSTRUCTION BYTE ADDRESS 8 7 6 5 4 3 1 9TH BIT OF ADDRESS DATA IN 7 6 5 4 3 1 SO HIGH IMPEDANCE HOLD Timing CS SCK t CD t CD t HD HOLD t HD t HZ SO t LZ 11
AT51 Ordering Information t WP (max) (ms) I CC (max) (µa) I SB (max) (µa) 1 6 1 AT51-1PC AT51N-1SC 1 AT51-1PI AT51N-1SI 1 3 1 1 AT51-1PC-.7 AT51N-1SC-.7 1 1 AT51-1PI-.7 AT51N-1SI-.7 1 3 1 5 AT51-1PC-1.8 AT51N-1SC-1.8 1 5 AT51-1PI-1.8 AT51N-1SI-1.8 f MAX (khz) Ordering Code Package Operation Range ( C to 7 C) (-4 C to 85 C) ( C to 7 C) (-4 C to 85 C) ( C to 7 C) (-4 C to 85 C) Package Type 8-Lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-Lead,.15" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Optio Blank Standard Device (4.5V to 5.5V) -.7 Low Voltage (.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V) 1 AT51//4
AT51//4 AT5 Ordering Information t WP (max) (ms) I CC (max) (µa) I SB (max) (µa) 1 6 1 1 AT5-1PC AT5N-1SC 1 1 AT5-1PI AT5N-1SI 1 3 1 1 AT5-1PC-.7 AT5N-1SC-.7 1 1 AT5-1PI-.7 AT5N-1SI-.7 1 3 1 5 AT5-1PC-1.8 AT5N-1SC-1.8 1 5 AT5-1PI-1.8 AT5N-1SI-1.8 f MAX (khz) Ordering Code Package Operation Range ( C to 7 C) (-4 C to 85 C) ( C to 7 C) (-4 C to 85 C) ( C to 7 C) (-4 C to 85 C) Package Type 8-Lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-Lead,.15" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Optio Blank Standard Device (4.5V to 5.5V) -.7 Low Voltage (.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V) 13
AT54 Ordering Information t WP (max) (ms) I CC (max) (µa) I SB (max) (µa) 1 6 1 1 AT54-1PC AT54N-1SC 1 1 AT54-1PI AT54N-1SI 1 3 1 1 AT54-1PC-.7 AT54N-1SC-.7 1 1 AT54-1PI-.7 AT54N-1SI-.7 1 3 1 5 AT54-1PC-1.8 AT54N-1SC-1.8 1 5 AT54-1PI-1.8 AT54N-1SI-1.8 f MAX (khz) Ordering Code Package Operation Range ( C to 7 C) (-4 C to 85 C) ( C to 7 C) (-4 C to 85 C) ( C to 7 C) (-4 C to 85 C) Package Type 8-Lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-Lead,.15" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Optio Blank Standard Device (4.5V to 5.5V) -.7 Low Voltage (.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V) 14 AT51//4
AT51//4 Packaging Information, 8-Lead,.3" Wide, Plastic Dual Inline Package (PDIP) Dimeio in Inches and (Millimeters) JEDEC STANDARD MS-1 BA, 8-Lead,.15" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimeio in Inches and (Millimeters).4 (1.16).355 (9.). (.58).13 (.33) PIN 1.8 (7.11).4 (6.1) PIN 1.157 (3.99).15 (3.81).44 (6.).8 (5.79).3 (7.6) REF.37 (.94).7 (.69).5 (1.7) BSC.1 (5.33) MAX SEATING PLANE.15 (3.81).115 (.9).1 (.35).8 (.3).7 (1.78).45 (1.14).1 (.54) BSC.15 (.38) MIN. (.559).14 (.356).35 (8.6).3 (7.6) 15 REF.43 (1.9) MAX.196 (4.98).189 (4.8).1 (.54).4 (.1).68 (1.73).53 (1.35) REF.1 (.54) 8.7 (.3).5 (1.7).16 (.46) 15
Atmel Headquarters Corporate Headquarters 35 Orchard Parkway San Jose, CA 95131 TEL (48) 441-311 FAX (48) 487-6 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 176-686677 FAX (44) 176-686697 Atmel Operatio Atmel Colorado Springs 115 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 896 TEL (719) 576-33 FAX (719) 54-1759 Atmel Rousset Zone Industrielle 1316 Rousset Cedex, France TEL (33) 4 4 53 6 FAX (33) 4 4 53 6 1 Asia Atmel Asia, Ltd. Room 119 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon, Hong Kong TEL (85) 719778 FAX (85) 71369 Japan Atmel Japan K.K. Tonetsu Shinkawa Bldg., 9F 1-4-8 Shinkawa Chuo-ku, Tokyo 14-33 Japan TEL (81) 3-353-3551 FAX (81) 3-353-7581 Fax-on-Demand North America: 1-(8) 9-8635 International: 1-(48) 441-73 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(48) 436-439 Atmel Corporation 1998. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditio located on the Company s website. The Company assumes no respoibility for any errors which may appear in this document, reserves the right to change devices or specificatio detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licees to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 66E 8/98/xM