Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni Department of Computer Science Columbia University in the City of New York NSF Workshop on Emerging Technologies for Interconnect Washington DC Feb 2 3, 2012
The Emerging IT Scene and The Rise of Heterogeneous Computing Source: J. Rabaey From the Edge of the Cloud to its Infrastructural Core the most critical challenges are in the Integration, Programming and Management of Heterogeneous Components Heterogeneous Computing is emerging in cyber physical systems multi core system on chip (SoC) platforms cloud computing integration of emerging technologies
Perspective: Which Platform Architecture in the Year 2020? 47M transistors in a die under 25 mm sq 9 metal 45nm low leakage CMOS dual threaded in order pipelined CPU dissipates 2W while running at 2Ghz Various I/O Heterogeneous Multi Core Systems on Chip emerge as the fundamental computing platform Sensors Radio Analog Signal Processing
Communication Based Design At run time, it is not only a communication medium for energy efficient exchange of massive data among cores but also a distributed mechanism to manage on chip resources and control SoC operations Must be pervasive reaching every chip corner but low key limited impact design budget Key role at design time in simplifying reuse and integration of components Communication & Control Infrastructure I/O Ports Sensors Radio Analog Signal Processing
The Evolution of Traditional Electronic Design Automation Flow System Level Specification Computation Logic System Level Design Interface Flexible, Synthesizable RTL Representation Logic and Physical Design Placement Communication Routing soft IPs hard IPs module views activity inputs OA comm. lib program. blocks block views parasitics System Level Simulation and Analysis Floorplanning and Wireplanning Estimations for Area, Power, Performance Interconnect Timing/Power Analysis Full Chip Analysis Physical Implementation
System Level Design Abstraction Layers TLM Untimed Loosely Timed Approximately Timed Cycle Accurate Application Programming Computation System Level Specification System Level Design Software Design Virtual Platforms for Early Hardware/Software Integration Interface Design Space Exploration Flexible, Synthesizable RTL Representation Hardware Design Communication Complex application scenarios Virtual platforms Successive refinements Design space exploration driven
Robust System Level Design: A Tale of Two Principles Formal Specification of the Target Application Constraints Propagation Perf. / Cost Abstractions Library of Reusable Components Application Space Separation of Concerns the various aspects of design are decoupled along orthogonal axes to explore alternative solutions more effectively Correct by Construction Design the system is built through a sequence of precise steps to combine simpler components into more complex ones while constraining their interactions to preserve key properties (compositionality) this may restrict the searchable solution space (optimality/robustness trade off) Implementation Space (Platform) Final Implementation
Heterogeneous Electronic/Photonic NoC as a Subsystem of Future 3D Integrated Circuits photonic NoC 3D memory layers multi core processor layer A. Shacham, K. Bergman and L.P. Carloni, Photonic Networks on Chip for Future Generations of Chip Multi Processors, IEEE Transactions on Computers, September 2008
Computer Aided Design of Silicon Photonic Interconnection Networks Photonic devices are fundamentally different and still evolving Need for better coordination between device researchers and network/architecture researchers Methodologies and tools for chip scale photonic interconnection networks Physical Characterizations Insertion Loss Throughput Extinction Ratio Sensitivity Device Fabrication and Test Network Design and Simulation Bit Error Rate Scalability Nonlinearity Performance Measurements Power
PhoenixSim: a CAD Environment for Analysis and Optimization of Chip Scale Photonic Networks Photonic Elements Coupler Interconnection Network Fabric Electronic Elements Crossbar Switch Arbiter Logic System Level Analysis and Simulation...... Route Logic PSE control Resource Allocation Input Buffer Wire J. Chan, G. Hendry, A. Biberman, K. Bergman and L.P. Carloni, PhoenixSim: A Simulator for Luca Physical Layer Carloni Columbia Analysis University of Chip Scale Photonic Interconnection Networks, DATE 2010
Network Modeling and Analysis in the PhoenixSim Design Environment The physical properties that are identified at Step 4 have an impact on network functionality and scalability and play a crucial role in determining overall system performance Iterative process: the performance results and analysis of the modeled network can be used to refine the topology design and device parameters to further optimize the overall performance
New Generation of CAD Tools is Needed Integrated CAD environments must capture key parameters insertion loss, extinction ratio, thermal dependency and the effects of their combination impact of waveguide crossings on network topology Support modeling/analysis across abstraction layers system level / behavioral micro architectural / structural physical Interoperability among tools, models key to develop effective common metrics and benchmark for this interdisciplinary community
Conclusions Silicon Photonics the last few years have seen major breakthroughs in the fabrication of all the devices necessary to build chip scale interconnection networks Another Facet of the Age of Heterogeneous Computing to combine the best of both worlds (electronic and photonic) is critical to build networks that overcome the power and memory walls Exciting Inter Disciplinary Research Area to realize the promise of chip scale photonic communication requires the support of vertically integrated research programs combining researchers in devices, networks, architectures, applications, and CAD tools/methodologies