Single Cycle CPU Design Mehran Rezaei
What does it mean? Instruction Fetch Instruction Memory clk pc 32 32 address add $t,$t,$t2 instruction Next Logic to generate the address of next instruction
The Branch Instruction beq rs, rt, imm6 mem[pc] Fetch the instruction from memory Equal <- R[rs] == R[rt] Calculate the branch condition if (COND) Calculate the next instruction s address PC <- PC + 4 + ( SignExt(imm6) x 4 ) else PC <- PC + 4
Next addr generation branch arch if branch taken pc branch target address else pc pc + 4 instruction imm 6 extend 32 pc 4 32 32 Shift left 2 + 32 32 32 + mux pc zero extension sign extension Branch taken
... Instruction Decode/Operand Fetch Next address pc Instruction 32 RS=2 RT=3 RD=5 5 5 5 Register file 6 32 32 busa 6 busb clk add $5,$2,$3
... Execution Next address 5 32 pc Instruction 5 5 6 32 32 6 result add clk add $5,$2,$3
... Write Back Next address pc Instruction RD=5 6 6 busa busb 6 result clk busw add $5,$2,$3
... Or immediate ORI R[rt] < R[rs] zero_ext(imm6);pc < PC + 4 Next address RgDst ALUsrc 5 pc Instruction 6 5 5 32 ALU 32 ext 32 ALUop EXop
... Load LOAD R[rt] < MEM[ R[rs] + sign_ext(imm6)];pc < PC + 4 Next address RgDst ALUsrc MemtoReg pc Instruction ALU Read data ext ALUop EXop MemRead
... Store STORE MEM[ R[rs] + sign_ext(imm6) ] < R[rt];PC < PC + 4 Next address RgDst ALUsrc MemWrite MemtoReg pc Instruction ALU Write data Read data ext ALUop EXop MemRead
... BEQ if ( R[rs] == R[rt] ) then PC < PC + 4 + [sign_ext(imm6) ] else PC < PC + 4 4 + Branch Shift Left 2 + RgDst ALUsrc MemWrite MemtoReg zero pc Instruction ALU Write data Read data ext ALUop cp EXop MemRead
4 Shift Left 2 Branch pc Opcode Instruction ExtOp Cont Unit RegWrite RegDst Read Addr Read Addr2 Write Addr Write Data ALUSrc Read Data Read Data2 MemWrite OVF Zero ALUCtr MemtoReg Write Data MemRead Read Data Funct Extension ALUOp ALU Cont
4 Shift Left 2 Branch pc Opcode Instruction ExtOp Cont Unit RegWrite RegDst Read Addr Read Addr2 Write Addr Write Data ALUSrc Read Data Read Data2 MemWrite OVF Zero or ALUCtr MemtoReg Write Data MemRead Read Data Funct Extension ALUOp ALU Cont ORI R[rt] < R[rs] zero_ext(imm6);pc < PC + 4
An Abstract View Inst. Mem Control Unit Instruction<3:> Datapath
4 Shift Left 2 Branch pc Instruction Opcode ExtOp Cont Unit RegWrite ALUSrc RegDst Read Addr Read Addr2 Write Addr Write Data Read Data Read Data2 MemWrite OVF Zero ALUCtr MemtoReg MemRead Write Data Rea d Data Extension ALUOp Funct ALU Cont
The control system alone Branch Opcode Cont Unit RegWrite ALUSrc MemWrite MemtoReg MemRead RegDst ExtOp ALUCtr ALUOp Funct ALU Cont
A Summary of the Control Signals See func We Don t Care :-) Appendix A op add sub ori lw sw beq addi RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUctr<2:> x Add x Subtract Or Add x x Add x x x Subtract Add 3 26 2 6 6 R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq,addi J-type op target address jump
The Concept of Local Decoding op R-type ori lw sw beq addi RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop<N:> x R-type Or Add x x Add x x x Subtract Add op 6 Main Control func 6 ALUop 3 ALU Control (Local) ALUctr 3 ALU
PLA Implementation of the Main Control minus ALUop... <>.. <>.. <>.. <>. <>.. op<> R-type ori lw sw beq addi RegWrite ALUSrc RegDst MemtoReg MemWrite Branch ExtOp
The Truth Table for the Main Control op 6 Main Control RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) RegDst ALUSrc : ALUop 3 func 6 ALU Control (Local) ALUctr 3 op R-type ori lw sw beq addi x x x x x x R-type Or Add Add Subtract Add ALUop <2> ALUop <> ALUop <>
The Truth Table for RegWrite op RegWrite = R-type + ori + lw + addi R-type ori lw sw beq addi RegWrite =! &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +! &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) +! &!op<4> & op<3> & &!op<2> &!op<> &!op<> (addi).... <> <>.. <>.. <>.. <>.. op<> R-type ori lw sw beq addi RegWrite
PLA Implementation of the Main Control.......... <> <> <> <> <>.. op<> R-type ori lw sw beq addi RegWrite ALUSr c RegDst MemtoReg MemWrite Branch ExtOp ALUop<2> ALUop<> ALUop<>
The ALU control system ALUctr 3 6 Function ALU Control 3 ALUopt
ALU control unit s truth table + + output input input operation TYPE ALUctr ALUopt opcode function ADD R "" "" "" "" ADD I "" "" addi+lw +sw XXXXXXX SUB R "" "" "" "" SUB I "" "" beq+bne XXXXXXX OR R "" "" "" "" OR I "" "" "" XXXXXXX AND R "" "" "" "" SLT R "" "" "" "" + Not part of the table
ALU control unit s truth table (cont d) Input Output operation TYPE ALUopt function ALUctr ADD R ADD I XXXXXXX SUB R SUB I XXXXXXX OR R OR I XXXXXXX AND R SLT R
ALU control unit s truth table (cont d) Input Output operation TYPE ALUopt function ALUctr ADD R SUB R OR R AND R SLT R ADD I XXXXXXX SUB I XXXXXXX OR I XXXXXXX
The logic of ALU control unit 6 Function X 3 3 3 3 ALUctr ALUopt ALUopt<2> ALU Control
X truth table operation function ALUctr ADD "" "" SUB "" "" OR "" "" AND "" "" SLT "" "" ALUctr<2> = F<5> &!F<4> &!F<> (!F<3> & F<2> &!F<> + F<3> &!F<2> & F<>) ALUctr<> = ALUctr<2> + F<5> &!F<4> &!F<3> & F<2> &!F<> & F<> ALUctr<> = F<5> &!F<4> &!F<2> & F<> &!F<>