Major CPU Design Steps

Transcription

1 Datapath Major CPU Design Steps. Analyze instruction set operations using independent RTN ISA => RTN => datapath requirements. This provides the the required datapath components and how they are connected to meet ISA requirements.. Select required datapath components, connections & establish clock methodology (e.g clock edge-triggered). + Determine number of cycles per instruction and operations in each cycle. 3. Assemble datapath meeting the requirements. Control 4. Identify and define the function of all control points or signals needed by the datapath. Analyze implementation of each instruction to determine setting of control points that affects its operations and register transfer. 5. Design & assemble the control logic. Hard-Wired: Finite-state machine implementation. Microprogrammed. i.e using a control program 3 rd Edition Chapter 5.5 See Handout Not in 4 th Edition # Lec # 5 Winter

2 Single Cycle MIPS Datapath: CPI =, Long Clock Cycle Branch Zero imm6 4 PC Ext PC+4 Adder Adder PCSrc 0 Mux Branch Target Jump Not Included Clk Inst Memory 00 PC Adr RegDst RegWr busw Clk Rs imm6 <:5> Rd 0 Rt 5 5 Rs 5 Rw Ra Rb -bit Registers 6 (Includes ORI not in book version) Rt <6:0> Rd <:5> Rt busa busb Extender ExtOp <0:5> Imm6 R[rt] Zero R[rs] 0 Mux ALUSrc Instruction<3:0> Function Field ALUop (-bits) ALU Control = ALU Main ALU MemWr WrEn Adr Data In Data Memory Clk T = I x CPI x C MemtoReg # Lec # 5 Winter Mux

3 Single Cycle MIPS Datapath Extended To Handle Jump with Control Unit Added 4 Add Instruction [5 0] Shift left Jump address [3 0] 6 8 PC +4 PC + 4 [3 8] 4 PC +4 Add ALU result PC +4 Branch Target 0 M u x 0 M u x Opcode Instruction [3 6] Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Shift left Book figure may have an error! PC Read address Instruction [3 0] Instruction memory Figure 5.4 page 34 Instruction [5 ] Instruction [0 6] Instruction [5 ] Instruction [5 0] imm6 rd rs rt 0 M u x Read register Read register Write register Write data Read data Read data Registers 6 Sign extend Function Field Instruction [5 0] R[rs] R[rt] 0 M u x ALU control ALU Zero ALU result R[rt] Address Write data ALUOp (-bits) 00 = add 0 = subtract 0 = R-Type Data memory Read data M u x 0 In this book version, ORI is not supported no zero extend of immediate needed. #3 Lec # 5 Winter

4 Drawbacks of Single-Cycle Processor. Long cycle time: CPI = All instructions must take as much time as the slowest: Cycle time for load is longer than needed for all other instructions. Real memory is not as well-behaved as idealized memory Cannot always complete data access in one (short) cycle.. Impossible to implement complex, variable-length instructions and complex addressing modes in a single cycle. e.g indirect memory addressing. 3. High and duplicate hardware resource requirements Any hardware functional unit cannot be used more than once in a single cycle (e.g. ALUs). 4. Cannot pipeline (overlap) the processing of one instruction with the previous instructions. (instruction pipelining, chapter 6). #4 Lec # 5 Winter

5 Abstract View of Single Cycle CPU op Main Control fun ALU control Branch, Jump Equal ExtOp ALUSrc ALUctr MemRd MemWr ns RegDst RegWr MemWr Next PC PC Instruction Fetch ns Register Fetch ns Ext ns ALU Mem Access ns Reg. Wrt Data Mem Result Store One CPU Clock Cycle Duration C = 8ns One instruction per cycle CPI = Assuming the following datapath/control hardware components delays: Memory Units: ns ALU and adders: ns Register File: ns Control Unit < ns #5 Lec # 5 Winter

6 Single Cycle Instruction Timing Arithmetic & Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory Reg File mux ALU Data Mem muxsetup Critical Path Store (Determines CPU clock cycle, C) PC Inst Memory Reg File mux ALU Data Mem Branch PC Inst Memory Reg File cmp mux Critical Path: Load (e.g 8 ns) #6 Lec # 5 Winter

7 Clock Cycle Time & Critical Path Clk One CPU Clock Cycle Duration C = 8ns here i.e longest delay Critical Path LW in this case Critical path: the slowest path between any two storage devices Clock Cycle time is a function of the critical path, and must be greater than: Clock-to-Q + Longest Delay Path through the Combination Logic + Setup + Clock Skew Assuming the following datapath/control hardware components delays: Memory Units: ns ALU and adders: ns Register File: ns Control Unit < ns #7 Lec # 5 Winter

8 Reducing Cycle Time: Multi-Cycle Design Cut combinational dependency graph by inserting registers / latches. The same work is done in two or more shorter cycles, rather than one long cycle. storage element storage element One long cycle e.g CPI = Acyclic Combinational Logic Two shorter cycles => Cycle Acyclic Combinational Logic (A) storage element e.g CPI = Storage Element: Register or memory storage element Cycle Acyclic Combinational Logic (B) Place registers to: Get a balanced clock cycle length Save any results needed for the remaining cycles storage element #8 Lec # 5 Winter

9 Basic MIPS Instruction Processing Steps Instruction Memory Instruction Fetch Next Instruction Instruction Decode Obtain instruction from program storage Instruction Mem[PC] Update program counter to address of next instruction Determine instruction type Obtain operands from registers Common steps for all instructions Execute Result Store Compute result value or status Store result in register/memory if needed (usually called Write Back). Done by Control Unit #9 Lec # 5 Winter

10 Partitioning The Single Cycle Datapath Add registers between steps to break into cycles Branch, Jump ns To Control Unit ns ExtOp ns ns ns ALUSrc ALUctr MemRd MemWr RegDst RegWr MemWr Next PC PC Instruction Fetch Cycle (IF) Instruction Fetch Operand Fetch Instruction Decode Cycle (ID) Exec Execution Cycle (EX) Mem Access Data Memory Access Cycle (MEM) Place registers to: Get a balanced clock cycle length Save any results needed for the remaining cycles Reg. File Data Mem Result Store Write back Cycle (WB) #0 Lec # 5 Winter

11 Branch, Jump Next PC PC Example Multi-cycle Datapath Instruction Fetch To Control Unit IR Reg File A B ExtOp ALUSrc ALUctr Ext ALU R MemRd MemWr Mem Access Instruction Instruction Fetch Decode Execution (IF) (ID) (EX) Memory ns ns ns (MEM) 3 4 ns 5 M Data Mem MemToReg RegDst RegWr Reg. File Registers added: All clock-edge triggered (not shown register write enable control lines) IR: Instruction register A, B: Two registers to hold operands read from register file. R: or ALUOut, holds the output of the main ALU M: or Memory data register (MDR) to hold data read from data memory CPU Clock Cycle Time: Worst cycle delay = C = ns (ignoring MUX, CLK-Q delays) Assuming the following datapath/control hardware components delays: Memory Units: ns ALU and adders: ns Register File: ns Control Unit < ns Thus Clock Rate: f = / ns = 500 MHz Equal Write Back (WB) ns # Lec # 5 Winter

12 Operations (Dependant RTN) for Each Cycle R-Type Logic Immediate Load Store Branch IF Instruction Fetch IR Mem[PC] IR Mem[PC] IR Mem[PC] IR Mem[PC] IR Mem[PC] ID Instruction Decode A B R[rs] R[rt] A B R[rs] R[rt A B R[rs] R[rt A B R[rs] R[rt] A B R[rs] R[rt] Zero A - B If Zero = : EX Execution R A funct B R A OR ZeroExt[imm6] R A + SignEx(Im6) R A + SignEx(Im6) + (SignExt(imm6) x4) else (i.e Zero =0): MEM Memory M Mem[R] Mem[R] B WB Write Back R[rd] R R[rt] R R[rt] M Instruction Fetch (IF) & Instruction Decode cycles are common for all instructions # Lec # 5 Winter

13 MIPS Multi-Cycle Datapath: Five Cycles of Load CPI = 5 Cycle Cycle Cycle 3 Cycle 4 Cycle 5 Load IF ID EX MEM WB - Instruction Fetch (IF): Fetch the instruction from instruction Memory. - Instruction Decode (ID): Operand Register Fetch and Instruction Decode. 3- Execute (EX): Calculate the effective memory address. 4- Memory (MEM): Read the data from the Data Memory. 5- Write Back (WB): Write the loaded data to the register file. Update PC. #3 Lec # 5 Winter

14 Multi-cycle Datapath Instruction CPI R-Type/Immediate: Require four cycles, CPI = 4 IF, ID, EX, WB Loads: Require five cycles, CPI = 5 IF, ID, EX, MEM, WB Stores: Require four cycles, CPI = 4 IF, ID, EX, MEM Branches/Jumps: Require three cycles, CPI = 3 IF, ID, EX Average or effective program CPI: 3 CPI 5 depending on program profile (instruction mix). #4 Lec # 5 Winter

15 Clk Single Cycle Vs. Multi-Cycle CPU 8ns (5 MHz) Cycle Cycle Single Cycle Implementation: 8 ns Load Store Waste ns (500 MHz) Cycle Cycle Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 0 Clk Multiple Cycle Implementation: Load IF ID EX MEM WB Store IF ID EX MEM R-type IF T = I x CPI x C Single-Cycle CPU: CPI = C = 8ns f = 5 MHz One million instructions take = I x CPI x C = 0 6 x x 8x0-9 = 8 msec Assuming the following datapath/control hardware components delays: Memory Units: ns ALU and adders: ns Register File: ns Control Unit < ns Multi-Cycle CPU: CPI = 3 to 5 C = ns One million instructions take from 0 6 x 3 x x0-9 = 6 msec to 0 6 x 5 x x0-9 = 0 msec depending on instruction mix used. f = 500 MHz #5 Lec # 5 Winter

16 Control Unit Design: Finite State Machine (FSM) Control Model State specifies control points (outputs) for Register Transfer. Control points (outputs) are assumed to depend only on the current state and not inputs (i.e. Moore finite state machine) Transfer (register/memory writes) and state transition occur upon exiting the state on the falling edge of the clock. inputs (opcode, conditions) Last State Next State Logic Control State State X Register Transfer Control Points Current State e.g Flip-Flops Output Logic outputs (control points) To datapath Moore Finite State Machine State Transition Depends on Inputs Next State #6 Lec # 5 Winter

17 Control Specification For Multi-cycle CPU Finite State Machine (FSM) - State Transition Diagram IR MEM[PC] A R[rs] B R[rt] instruction fetch (Start state) decode / operand fetch Execute R-type R A fun B ORi R A or ZX LW R A + SX SW R A + SX BEQ & ~Zero BEQ & Zero PC PC + 4+ SX 00 Memory M MEM[R] MEM[R] B To instruction fetch R[rd] R R[rt] R R[rt] M 3 states: 4 State Flip-Flops needed Write-back To instruction fetch To instruction fetch #7 Lec # 5 Winter

18 Traditional FSM Controller state op cond next state control points Outputs Next State Logic Output Logic Inputs State Transition Table Equal 6 Opcode next State control points Current State 4 State Outputs (Control points) datapath State op State register (4 Flip-Flops) To datapath #8 Lec # 5 Winter

19 Traditional FSM Controller datapath + state diagram => control Translate RTN statements into control points. Assign states. Implement the controller. More on FSM controller implementation in Appendix C #9 Lec # 5 Winter

20 Mapping RTNs To Control Points Examples & State Assignments IR MEM[PC] 0000 imem_rd, IRen 0 instruction fetch ALUfun, Sen Aen, Ben A R[rs] B R[rt] 000 decode / operand fetch Execute Memory 4 R-type R A fun B 000 R[rd] R 00 RegDst, RegWr, PCen ORi R A or ZX 00 R[rt] R LW R A + SX 000 M MEM[R] 00 R[rt] M 00 SW R A + SX 0 MEM[R] B 00 BEQ & ~Zero 00 3 BEQ & Zero PC PC + 4+SX To instruction fetch state states: 4 State Flip-Flops needed Write-back To instruction fetch state 0000 To instruction fetch state 0000 #0 Lec # 5 Winter

21 IF ID BEQ R ORI LW SW Detailed Control Specification - State Transition Table Current Op field Z Next IR PC Ops Exec Mem Write-Back State en sel A B Ex Sr ALU S R W M M-R Wr Dst 0000??????? BEQ BEQ R-type x ori x LW x SW x xxxxxx x xxxxxx x xxxxxx x 00 0 fun Can be combined in one state 00 xxxxxx x xxxxxx x or 0 xxxxxx x xxxxxx x 00 0 add 00 xxxxxx x xxxxxx x xxxxxx x 00 0 add 00 xxxxxx x More on FSM controller implementation in Appendix C # Lec # 5 Winter

22 Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: memory, ALU PCWr PC IorD 0 Mux PCWrCond Zero MemWr Address Ideal Memory Din Dout MemRd IRWr Instruction Reg Mem Data Reg RegDst Rs Rt Rt Rd Mux Mux 0 RegWr Ra Rb busa Reg File Rw buswbusb A B ALUSrcA PC 4 PCSrc 0 Mux 0 3 Mux 0 Zero ALU ALU Control ALU Out Imm 6 Extend << MemtoReg ALUSrcB ALUOp # Lec # 5 Winter

23 Alternative Multiple Cycle Datapath (In Textbook) IorD MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA PC 0 M u x Address Write data Memory MemData Instruction [5 ] Instruction [0 6] Instruction [5 0] Instruction register Instruction [5 0] Memory data register rs rt 0 M Instruction u [5 ] x rd 0 M u x 6 imm6 Read register Read register Registers Write register Write data Sign extend Read data Read data Shift left A B 4 0 M u x 0 M u x 3 ALU control ALU Zero ALU result ALUOut i.e MDR Instruction [5 0] MemtoReg ALUSrcB ALUOp Shared instruction/data memory unit A single ALU shared among instructions Shared units require additional or widened multiplexors Temporary registers to hold data between clock cycles of the instruction: Additional registers: Instruction Register (IR), Memory Data Register (MDR), A, B, ALUOut (Figure 5.7 page ) #3 Lec # 5 Winter

24 Alternative Multiple Cycle Datapath With Control Lines (Fig 5.8 In Textbook) PC PC+ 4 rt rs Branch Target rd imm6 (ORI not supported, Jump supported) (Figure 5.8 page 3) #4 Lec # 5 Winter

25 Signal Name RegDst RegWrite ALUSrcA MemRead MemWrite MemtoReg IorD IRWrite The Effect of The -bit Control Signals Effect when deasserted (=0) The register destination number for the write register comes from the rt field (instruction bits 0:6). None The first ALU operand is the PC None None The value fed to the register write data input comes from ALUOut register. The PC is used to supply the address to the memory unit. None Effect when asserted (=) The register destination number for the write register comes from the rd field (instruction bits 5:). The register on the write register input is written with the value on the Write data input. The First ALU operand is register A (i.e R[rs]) Content of memory specified by the address input are put on the memory data output. Memory contents specified by the address input is replaced by the value on the Write data input. The value fed to the register write data input comes from data memory register (MDR). The ALUOut register is used to supply the the address to the memory unit. The output of the memory is written into Instruction Register (IR) PCWrite PCWriteCond None None The PC is written; the source is controlled by PCSource The PC is written if the Zero output of the ALU is also active. (Figure 5.9 page 4) #5 Lec # 5 Winter

26 Signal Name The Effect of The -bit Control Signals Value (Binary) Effect ALUOp The ALU performs an add operation The ALU performs a subtract operation The funct field of the instruction determines the ALU operation (R-Type) The second input of the ALU comes from register B (i.e R[rs]) ALUSrcB PCSource 0 0 (Figure 5.9 page 4) The second input of the ALU is the constant 4 The second input of the ALU is the sign-extended 6-bit immediate (imm6) field of the instruction in IR The second input of the ALU is is the sign-extended 6-bit immediate field of IR shifted left bits (for branches) Output of the ALU (PC+4) is sent to the PC for writing The content of ALUOut (the branch target address) is sent to the PC for writing The jump target address (IR[5:0] shifted left bits and concatenated with PC+4[3:8] is sent to the PC for writing i.e jump address #6 Lec # 5 Winter

27 Operations (Dependant RTN) for Each Cycle R-Type Load Store Branch Jump IF Instruction Fetch IR Mem[PC] IR Mem[PC] IR Mem[PC] IR Mem[PC] IR Mem[PC] ID Instruction Decode A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) EX Execution ALUout A funct B ALUout A + SignEx(Imm6) ALUout A + SignEx(Imm6) Zero A - B Zero: PC ALUout PC Jump Address MEM Memory MDR Mem[ALUout] Mem[ALUout] B WB Write Back R[rd] ALUout R[rt] MDR Instruction Fetch (IF) & Instruction Decode (ID) cycles are common for all instructions #7 Lec # 5 Winter

28 High-Level View of Finite State Machine Control (Figure 5.) (Figure 5.33) (Figure 5.34) (Figure 5.35) (Figure 5.36) First steps are independent of the instruction class Then a series of sequences that depend on the instruction opcode Then the control returns to fetch a new instruction. Each box above represents one or several state. (Figure 5.3 page 3) #8 Lec # 5 Winter

29 FSM State Transition Diagram (From Book) IF ID (Figure 5.38 page 339) IR Mem[PC] A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) ALUout A + SignEx(Imm6) EX PC Jump Address ALUout A func B MDR Mem[ALUout] Zero A -B Zero: PC ALUout MEM WB R[rd] ALUout R[rt] WB MDR Mem[ALUout] B Total 0 states More on FSM controller implementation in Appendix C #9 Lec # 5 Winter

30 Instruction Fetch (IF) and Decode (ID) IR Mem[PC] FSM States IF A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) ID (Figure 5.33) (Figure 5.34) (Figure 5.35) (Figure 5.36) (Figure 5. page 333) #30 Lec # 5 Winter

31 Instruction Fetch (IF) Cycle (State 0) IR Mem[PC] MemRead = ALUSrcA = 0 IorD = 0 IRWrite = ALUSrcB = 0 ALUOp = 00 (add) PCWrite = PCSource = PC 0 0 PC+ 4 rt rs Branch Target rd imm6 00 Add (ORI not supported, Jump supported) (Figure 5.8 page 3) #3 Lec # 5 Winter

32 Instruction Decode (ID) Cycle (State ) A R[rs] B R[rt] ALUSrcA = 0 ALUSrcB = ALUOp = 00 (add) ALUout PC + (SignExt(imm6) x4) (Calculate branch target) PC 0 PC+ 4 rt rs Branch Target rd imm6 00 Add (ORI not supported, Jump supported) (Figure 5.8 page 3) # Lec # 5 Winter

33 Load/Store Instructions FSM States (From Instruction Decode) EX ALUout A + SignEx(Imm6) i.e Effective address calculation MDR Mem[ALUout] MEM Mem[ALUout] B R[rt] MDR WB (Figure 5.33 page 334) To Instruction Fetch (Figure 5.) #33 Lec # 5 Winter

34 Load/Store Execution (EX) Cycle (State ) Effective address calculation ALUout A + SignEx(Imm6) ALUSrcA = ALUSrcB = 0 ALUOp = 00 (add) PC 0 PC+ 4 rt rs Branch Target rd imm6 00 Add (ORI not supported, Jump supported) (Figure 5.8 page 3) #34 Lec # 5 Winter

35 Load Memory (MEM) Cycle (State 3) MDR Mem[ALUout] MemRead = IorD = PC PC+ 4 rt rs Branch Target rd imm6 (ORI not supported, Jump supported) (Figure 5.8 page 3) #35 Lec # 5 Winter

36 Load Write Back (WB) Cycle (State 4) R[rt] MDR RegWrite = MemtoReg = RegDst = 0 PC PC+ 4 rt rs 0 Branch Target rd imm6 (ORI not supported, Jump supported) (Figure 5.8 page 3) #36 Lec # 5 Winter

37 Store Memory (MEM) Cycle (State 5) Mem[ALUout] B MemWrite = IorD = PC PC+ 4 rt rs Branch Target rd imm6 (ORI not supported, Jump supported) (Figure 5.8 page 3) #37 Lec # 5 Winter

38 (From Instruction Decode) R-Type Instructions FSM States EX ALUout A funct B WB R[rd] ALUout (Figure 5.34 page 335) To State 0 (Instruction Fetch) (Figure 5.) #38 Lec # 5 Winter

39 R-Type Execution (EX) Cycle (State 6) ALUout A funct B ALUSrcA = ALUSrcB = 00 ALUOp = 0 (R-Type) PC 00 PC+ 4 rt rs Branch Target rd imm6 0 R-Type (ORI not supported, Jump supported) (Figure 5.8 page 3) #39 Lec # 5 Winter

40 R-Type Write Back (WB) Cycle (State 7) R[rd] ALUout RegWrite = MemtoReg = 0 RegDst = PC PC+ 4 rt rs Branch Target rd 0 imm6 (ORI not supported, Jump supported) (Figure 5.8 page 3) #40 Lec # 5 Winter

41 Branch Instruction Single EX State Jump Instruction Single EX State (From Instruction Decode) (From Instruction Decode) EX Zero A - B Zero : PC ALUout EX PC Jump Address To State 0 (Instruction Fetch) (Figure 5.) To State 0 (Instruction Fetch) (Figure 5.) (Figures 5.35, 5.36 page 337) #4 Lec # 5 Winter

42 Zero A - B Zero : PC Branch Execution (EX) Cycle (State 8) ALUout ALUSrcA = ALUSrcB = 00 ALUOp = 0 (Subtract) PCWriteCond = PCSource = 0 0 PC 00 PC+ 4 rt rs Branch Target rd imm6 0 Subtract (ORI not supported, Jump supported) (Figure 5.8 page 3) #4 Lec # 5 Winter

43 Jump Execution (EX) Cycle (State 9) PC Jump Address PCWrite = PCSource = 0 0 PC PC+ 4 rt rs Branch Target rd imm6 (ORI not supported, Jump supported) (Figure 5.8 page 3) #43 Lec # 5 Winter

44 MIPS Multi-cycle Datapath Performance Evaluation What is the average CPI? State diagram gives CPI for each instruction type. Workload (program) below gives frequency of each type. Type CPI i for type Frequency CPI i x freqi i Arith/Logic 4 40%.6 Load 5 30%.5 Store 4 0% 0.4 branch 3 0% 0.6 Average CPI: 4. Better than CPI = 5 if all instructions took the same number of clock cycles (5). T = I x CPI x C #44 Lec # 5 Winter

45 Adding Support for swap to Multi Cycle Datapath You are to add support for a new instruction, swap that exchanges the values of two registers to the MIPS multicycle datapath of Figure 5.8 on page swap $rs, $rt R[rt] Swap used the R-Type format with: R[rs] the value of field rs = the value of field rd R[rs] R[rt] Add any necessary datapaths and control signals to the multicycle datapath. Find a solution that minimizes the number of clock cycles required for the new instruction without modifying the register file. Justify the need for the modifications, if any. i.e No additional register write ports Show the necessary modifications to the multicycle control finite state machine of Figure 5.38 on page 339 when adding the swap instruction. For each new state added, provide the dependent RTN and active control signal values. #45 Lec # 5 Winter

46 Adding swap Instruction Support to Multi Cycle Datapath Swap $rs, $rt R[rt] R[rs] op rs rt R[rs] R[rt] rd [3-6] [5-] [0-6] [0-6] We assume here rs = rd in instruction encoding PC+ 4 rs rt R[rs] Branch Target rd imm6 3 R[rt] The outputs of A and B should be connected to the multiplexor controlled by MemtoReg if one of the two fields (rs and rd) contains the name of one of the registers being swapped. The other register is specified by rt. The MemtoReg control signal becomes two bits. #46 Lec # 5 Winter

47 Adding swap Instruction Support to Multi Cycle Datapath IF IR Mem[PC] ID A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) EX ALUout A + SignEx(Imm6) WB R[rd] B ALUout A func B Zero A -B Zero: PC ALUout WB R[rt] A R[rd] ALUout MEM WB Swap takes 4 cycles WB #47 Lec # 5 Winter

48 Adding Support for add3 to Multi Cycle Datapath You are to add support for a new instruction, add3, that adds the values of three registers, to the MIPS multicycle datapath of Figure 5.8 on page For example: add3 $s0,$s, $s, $s3 Register $s0 gets the sum of $s, $s and $s3. The instruction encoding uses a modified R-format, with an additional register specifier rx added replacing the five low bits of the funct field. 6 bits [3-6] 5 bits [5-] 5 bits [0-6] 5 bits [5-] OP rs rt rd rx add3 $s $s $s0 Not used $s3 Add necessary datapath components, connections, and control signals to the multicycle datapath without modifying the register bank or adding additional ALUs. Find a solution that minimizes the number of clock cycles required for the new instruction. Justify the need for the modifications, if any. Show the necessary modifications to the multicycle control finite state machine of Figure 5.38 on page 339 when adding the add3 instruction. For each new state added, provide the dependent RTN and active control signal values. 6 bits [0-5] 5 bits [4-0] #48 Lec # 5 Winter

49 Add3 $rd, $rs, $rt, $rx R[rd] R[rs] + R[rt] + R[rx] add3 instruction support to Multi Cycle Datapath rx is a new register specifier in field [0-4] of the instruction No additional register read ports or ALUs allowed Modified R-Format op rs rt rd rx [3-6] [5-] [0-6] [0-6] [4-0] WriteB Re adsrc PC+ 4 rx rs rt Branch Target rd imm6. ALUout is added as an extra input to first ALU operand MUX to use the previous ALU result as an input for the second addition.. A multiplexor should be added to select between rt and the new field rx containing register number of the 3rd operand (bits 4-0 for the instruction) for input for Read Register. This multiplexor will be controlled by a new one bit control signal called ReadSrc. 3. WriteB control line added to enable writing R[rx] to B #49 Lec # 5 Winter

50 add3 instruction support to Multi Cycle Datapath IF IR Mem[PC] ID A R[rs] B R[rt] ALUout PC + (SignExt(imm6) x4) EX ALUout A + SignEx(Im6) WriteB EX WriteB ALUout B R[rx] A + B ALUout A func B Zero A -B Zero: PC ALUout EX ALUout ALUout + B MEM R[rd] ALUout WB Add3 takes 5 cycles WB #50 Lec # 5 Winter