CS 6C: Great Ideas in Computer Architecture (Machine Structures) Single- Cycle CPU Datapath & Control Part 2 Instructors: Krste Asanovic & Vladimir Stojanovic hfp://inst.eecs.berkeley.edu/~cs6c/
Review: Processor Design 5 steps Step : Analyze instrucqon set to determine datapath requirements Meaning of each instrucqon is given by register transfers Datapath must include storage element for ISA registers Datapath must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementaqon of each instrucqon to determine sewng of control points that realizes the register transfer Step 5: Assemble the control logic
Processor Design: 5 steps Step : Analyze instrucqon set to determine datapath requirements Meaning of each instrucqon is given by register transfers Datapath must include storage element for ISA registers Datapath must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the requirements Step 4: Analyze implementaqon of each instrucqon to determine sewng of control points that realizes the register transfer Step 5: Assemble the control logic
Register- Register Timing: One Complete Cycle (Add/Sub) Clk PC Old Value Rs,, Rd, Op, Func ALUctr New Value Old Value Old Value InstrucQon Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value ALU Delay busw Old Value New Value RegWr Rd Rs ALUctr 5 5 5 Register Write Rw Ra Rb busa busw Occurs Here RegFile busb ALU
Register- Register Timing: One Complete Cycle Clk PC Old Value Rs,, Rd, Op, Func ALUctr New Value Old Value Old Value InstrucQon Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value ALU Delay busw Old Value New Value RegWr Rd Rs ALUctr 5 5 5 Register Write Rw Ra Rb busa busw Occurs Here RegFile busb ALU
3c: Logical Op (or) with Immediate R[rt] = R[rs] op ZeroExt[imm6] RegDst RegWr Rd Rs 5 5 Rw imm6 Ra Rb RegFile 6 5 3 26 2 op rs rt immediate 3 6 bits 5 bits 5 bits 6 5 6 bits ZeroExt busa busb 6 bits ALUSrc ALUctr 6 immediate 6 bits Wri/ng to register (not Rd)!! ALU What about Read?
3d: Load OperaQons R[rt] = Mem[R[rs] + SignExt[imm6]] Example: lw rt,rs,imm6 3 26 2 6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst Rd RegWr Rs 5 5 5 Rw Ra Rb RegFile imm6 6 ZeroExt busa busb ALUSrc ALUctr ALU
3d: Load OperaQons R[rt] = Mem[R[rs] + SignExt[imm6]] Example: lw rt,rs,imm6 3 26 2 6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst RegWr busw Rd Rs 5 5 Rw imm6 Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr ALU MemtoReg Adr Data
3e: Store OperaQons Mem[ R[rs] + SignExt[imm6] ] = R[rt] Ex.: sw rt, rs, imm6 3 26 2 6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst RegWr busw Rd imm6 Rs 5 5 Rw Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data MemtoReg
3e: Store OperaQons Mem[ R[rs] + SignExt[imm6] ] = R[rt] Ex.: sw rt, rs, imm6 3 26 2 6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits RegDst RegWr busw Rd imm6 Rs 5 5 Rw Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data MemtoReg
3f: The Branch InstrucQon 3 26 op 2 rs 6 rt immediate 6 bits 5 bits 5 bits 6 bits beq rs, rt, imm6! mem[pc] Fetch the instrucqon from memory Equal = (R[rs] == R[rt]) Calculate branch condiqon if (Equal) Calculate the next instrucqon s address PC = PC + 4 + ( SignExt(imm6) x 4 ) else PC = PC + 4
Datapath for Branch OperaQons 3 beq rs, rt, imm6 26 2 6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits Datapath generates condiqon (Equal) Inst Address 4 PC Ext imm6 Adder Adder npc_sel Mux PC RegWr busw Rs 5 5 5 Rw Ra Rb RegFile busa busb Equal ALUctr Already have mux, adder, need special sign extender for PC, need equal compare (sub?) = ALU
Instruc3on Fetch Unit including Branch 3 26 2 op rs rt immediate if (Zero == ) then PC = PC + 4 + SignExt[imm6]*4 ; else PC = PC + 4 npc_sel Inst Adr 6 InstrucQon<3:> Equal MUX npc_sel ctrl How to encode npc_sel? Direct MUX select? imm6 4 PC Ext Adder Adder PC Mux Branch inst. / not branch inst. Let s pick 2nd opqon npc_sel zero? MUX x Q: What logic gate?
PuWng it All Together:A Single Cycle Datapath 4 PC Ext imm6 Adder Adder npc_sel Mux Inst PC Adr Rs RegDst Rd RegWr busw <2:25> imm6 <6:2> Rs 5 5 Rw Ra Rb RegFile 6 Rd 5 <:5> Extender busa busb ExtOp <:5> Imm6 Equal Instruction<3:> ALUSrc ALUctr = ALU Data In MemWr WrEn Adr Data MemtoReg
Clickers/Peer InstrucQon What new (pseudo)instrucqon would need no new datapath hardware? A: branch if reg==immediate B: add two registers and branch if result zero C: store with auto- increment of base address: sw rt, rs, offset // rs incremented by offset ater store D: shit let logical by one bit 4 PC Ext imm6 Adder Adder Inst Adr Rs npc_sel RegDst Rd Mux PC RegWr Rs 5 5 busw <2:25> imm6 <6:2> Rw Ra Rb RegFile 6 5 <:5> Rd Extender busa busb ExtOp <:5> Imm6 Equal Instruction<3:> ALUSrc ALUctr = ALU Data In MemtoReg MemWr WrEn Adr Data
Administrivia 6
imm6 Datapath Control Signals ExtOp: zero, sign ALUsrc: regb; immed ALUctr: ADD, SUB, OR MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register 4 PC Ext Adder Adder Inst Address npc_sel & Equal Mux PC RegDst RegWr busw Rd Rs 5 5 Rw imm6 Ra Rb RegFile 6 ExtOp 5 Extender busa busb ALUSrc ALUctr Data In ALU MemWr WrEn Adr Data MemtoReg
Given Datapath: RTL à Control InstrucQon<3:> Inst Adr <26:3> <:5> <2:25> <6:2> <:5> <:5> Op Fun Rs Rd Imm6 Control npc_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg DATA PATH
RTL: The Add InstrucQon 3 26 2 6 6 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[PC] Fetch the instrucqon from memory R[rd] = R[rs] + R[rt] The actual operaqon PC = PC + 4 Calculate the next instrucqon s address
InstrucQon Fetch Unit at the Beginning of Add! Fetch the instrucqon from InstrucQon memory: InstrucQon = MEM[PC] same for all instrucqons Inst InstrucQon<3:> 4 PC Ext Adder Adder npc_sel PC Mux Inst Address imm6
Single Cycle Datapath during Add! 3 26 2 op rs rt rd shamt funct R[rd] = R[rs] + R[rt] RegDst= Rd RegWr= busw 6 npc_sel=+4 Rs 5 5 Rw imm6 Ra Rb RegFile 6 5 ExtOp=x Extender busa busb instr fetch unit zero ALUSrc= 6 InstrucQon<3:> <2:25> Rs Rd Imm6 ALUctr=ADD MemtoReg= = Data In ALU <6:2> <:5> MemWr= WrEn Adr Data <:5>
InstrucQon Fetch Unit at End of Add PC = PC + 4 Same for all instrucqons except: Branch and Jump Inst 4 PC Ext npc_sel=+4 Adder Adder PC Mux Inst Address imm6
J- type RegDst = RegWr = busw Single Cycle Datapath during Jump 3 Clk op Rd imm6 26 Mux 25 New PC = { PC[3..28], target address, } 5 5 Rs 5 Rw Ra Rb x - bit Registers 6 ExtOp = Jump= npc_sel= busb Extender Clk busa target address ALUctr = Mux ALUSrc = InstrucOon Fetch Unit ALU Data In Clk Zero InstrucQon<3:> <2:25> WrEn <6:2> Rs Rd Imm6 TA26 MemtoReg = MemWr = Adr Data <:5> jump <:5> Mux <:25>
Single Cycle Datapath during Jump J- type 3 RegDst = x RegWr = busw Clk op Rd 26 Mux imm6 25 New PC = { PC[3..28], target address, } 5 5 Rs 5 Rw Ra Rb x - bit Registers 6 Jump= npc_sel=? busb Extender ExtOp = x Clk busa target address ALUctr =x Mux ALUSrc = x InstrucOon Fetch Unit ALU Data In Clk Zero InstrucQon<3:> <2:25> WrEn <6:2> Rs Rd Imm6 TA26 MemtoReg = x MemWr = Adr Data <:5> jump <:5> Mux <:25>
Instruc3on Fetch Unit at the End of Jump J- type New PC = { PC[3..28], target address, } Jump npc_sel Zero 3 op 26 25 Inst Adr target address InstrucQon<3:> jump npc_mux_sel 4 Adder PC Mux How do we modify this to account for jumps? imm6 Adder Clk
Instruc3on Fetch Unit at the End of Jump J- type New PC = { PC[3..28], target address, } Jump npc_sel Zero imm6 3 4 op 26 Adder 25 npc_mux_sel Adder Mux TA 26 target address 4 (MSBs) Mux Inst Clk PC Adr jump InstrucQon<3:> Query Can Zero sqll get asserted? Does npc_sel need to be? If not, what?
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P&H Figure 4.7
inst Summary of the Control Signals (/2)!Register Transfer! add!r[rd] R[rs] + R[rt]; PC PC + 4!!ALUsrc=RegB, ALUctr= ADD, RegDst=rd, RegWr, npc_sel= +4!! sub!r[rd] R[rs] R[rt]; PC PC + 4!!ALUsrc=RegB, ALUctr= SUB, RegDst=rd, RegWr, npc_sel= +4! ori!r[rt] R[rs] + zero_ext(imm6); PC PC + 4!!ALUsrc=Im, Extop= Z, ALUctr= OR, RegDst=rt,RegWr, npc_sel= +4! lw!r[rt] MEM[ R[rs] + sign_ext(imm6)]; PC PC + 4!!ALUsrc=Im, Extop= sn, ALUctr= ADD, MemtoReg, RegDst=rt, RegWr,!nPC_sel = +4! sw!mem[ R[rs] + sign_ext(imm6)] R[rs]; PC PC + 4!!ALUsrc=Im, Extop= sn, ALUctr = ADD, MemWr, npc_sel = +4! beq!if (R[rs] == R[rt]) then PC PC + sign_ext(imm6)]!else PC PC + 4!!nPC_sel = br, ALUctr = SUB!
Summary of the Control Signals (2/2) See func We Don t Care :- ) Appendix A op RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr<2:> add sub ori lw sw beq jump x Add x Subtract Or Add x x Add x x x Subtract x x x? x x R- type 3 26 2 6 6 op rs rt rd shamt funct add, sub I- type op rs rt immediate ori, lw, sw, beq J- type op target address jump
Boolean Expressions for Controller RegDst = add + sub ALUSrc = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw npcsel = beq Jump = jump ExtOp = lw + sw ALUctr[] = sub + beq (assume ALUctr is ADD, SUB, OR) ALUctr[] = or! Where:! rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op ~op, ori = ~op 5 ~op 4 op 3 op 2 ~op op lw = op 5 ~op 4 ~op 3 ~op 2 op op sw = op 5 ~op 4 op 3 ~op 2 op op beq = ~op 5 ~op 4 ~op 3 op 2 ~op ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op ~op! How do we implement this in gates? add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func ~func!
Controller ImplementaQon opcode func AND logic add sub ori lw sw beq jump OR logic RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump ExtOp ALUctr[] ALUctr[]
Summary: Single- cycle Processor Five steps to design a processor:. Analyze instrucqon set à datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeqng the requirements Processor Control Datapath 4. Analyze implementaqon of each instrucqon to determine sewng of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic EquaQons Design Circuits Input Output