ECE24 - Digital Sstems Universit of Toronto Lab 2: Introduction Computer-Aided Design Software, the DE2 Board and Simple Logic. Introduction The purpose of this eercise is to introduce the software tools and hardware that are used in the labs for this course. The main software tool is the Altera Quartus II Computer Aided Design (CAD) sstem, which we will use to design and implement logic circuits in an Altera FPGA chip. You will need to install that software on our computer (or use one of the Universit s computers) before ou can start this lab. The First Handout given on the course web page has a section on how to download the software and obtain a license, or ou ma use the DVD handed out in class. The FPGA chip is provided on the lab board used for this course, which is called the Altera DE2 Development and Education board. This board will be used for all of the remaining lab eercises in the course, and for the course project. The DE2 board contains man useful features for learning about logic circuits, including simple input and output mechanisms like switches and lights, and more complicated features like audio and video devices. This lab eercise will use onl the switches and lights that are provided on the bottom edge of the board, as illustrated in Figure, but other lab eercises and the course project will utilize more advanced features. A detailed description of the DE2 board can be found in the Universit Program section of Altera s website at www.altera.com. Figure. The Altera DE2 Development and Education board.
2. Preparation - MUST BE DONE PRIOR TO LAB PERIOD! There are two main parts to the preparation for this eercise: performing tutorials (which we estimate will take about 2 hours) and designing some logic circuits. You must perform the tutorials and do the circuit design before coming to the lab. You will be required to present the results of this work for marking at the beginning of the lab. The purpose of the tutorials is to introduce use of the Quartus II software and the DE2 board and to gain some more familiarit with basic digital logic.. Do the tutorial called Using Quartus II CAD Software, which is found in Appendi B of the course tetbook Fundamentals of Digital Logic with Verilog Design, 2 nd Edition. This edition of the tetbook must be used because the old edition is for a completel different version of the software. This tutorial describes the basic usage of Quartus II, such as creating design projects and compiling circuits. It shows two was of creating circuits: using schematic capture, in which ou essentiall draw a picture of each circuit that the software understands and then describing the same circuits in tetual form in a language called Verilog. It will be etremel important for ou to realize that the tetual form and schematic forms describe eactl the same thing. We use the tetual often because it is far more powerful and quicker, but it is eas to confuse with software, and so we repeat: the language is a wa to describe hardware circuits. B using both in this tutorial, hopefull this will be clear. 2. Do the first part of the tutorial called Implementing Circuits in Altera Devices, which is in section C. of the tetbook.. Do the tutorial Phsical Implementation in an FPGA, which is found in Appendi D. 4. Do the circuit design work indicated in Parts II to V. Create these circuits using Verilog. Bring a printed cop (pasted into our lab book) of all four of them. Warning: this is quite a bit of work, so be sure to leave about at least 2 hours for this part alone. All of the following material must be read for marking at the beginning of the lab, in our lab book:. A print-out of the schematic diagram and simulation results for the circuit described in Appendi B that ou created. 2. A print-out of the Quartus II project file (this file has the etension.qpf) for our schematic-based project. Your Verilog source code for the circuit in Appendi B 4. A print-out of the Quartus II project file for our Verilog-based project in Appendi B 5. A print-out of the Quartus II project file corresponding to section C. 6. A print-out of the Quartus II settings file (this file has the etension.qsf) for the project created in section D.2 It is strongl suggested that ou simulate all of the circuits that ou compile, to ensure that ou have designed them correctl.. Lab Work (which requires Preparation as indicated above) In the lab ou will have to implement and test circuits ou created in the preparation. The in-lab component of our lab grade will be based onl on the circuits ou create in parts IV and V of this eercise. However, to 2
be able to do those parts, ou ll have to have done parts I through III. Please inform our TA when ou have completed both parts IV and V to obtain our grade. To simplif some of the steps, a starter kit is provided on course website, located in the director: http://www.eecg.utoronto.ca/ jaar/ece24_7f/lab2_starterkit.zip The starter kit is a ZIP archive containing a Quartus II project for each part of the lab. Unzip the archive into a working director called lab2. If ou use Windows Eplorer to view the contents of the lab2 director, ou should see the folders shown in Figure 2. Figure 2. The contents of the starter kit. Part I Download the circuits ou designed in the tutorial preparation onto the Altera DE2 board and test to see that the work. Part II Create a simple circuit to connect four switches to four lights on the Altera DE2 board, b etending the following Verilog code: // Simple module that connects the SW switches to the LEDR lights module part2 (Switch, Switch 2, Switch, Switch 4, Light, Light 2, Light, Light 4); input Switch, Switch 2, Switch, Switch 4; // toggle switches output Light, Light 2, Light, Light 4; // lights // Your code goes here endmodule Figure. Verilog code for Part II. The DE2 board has hardwired connections between the pins on its FPGA chip and the switches and lights on the board. To make use of these switches and lights ou have to tell Quartus II which of the signals in our Verilog code should be connected to which pins on the FPGA chip. The procedure for doing this is called pin assignment and was covered in the tutorial in Appendi D of the tetbook. For this part ou need to make pin assignments according to the following table:
Function Switch Switch 2 Switch Switch 4 Light Light 2 Light Light 4 Altera Cclone II Pin on the DE2 PIN N25 PIN N26 PIN P25 PIN AE4 PIN AE2 PIN AF2 PIN AB2 PIN AC22 Table : Pin assignment table for lights and switches in Part II. Perform the following steps.. The project for this part is provided in the starter kit. Open in Quartus II (using the command File > Open Project) the project named part2.qpf in the part2 subdirector to begin our work. 2. Create a Verilog module named part2 for the code in Figure and include it in our project. Make sure to complete the code b adding the assignment statements for the lights.. Use Quartus II to make the pin assignments shown in the above table. Compile the project. 4. Download the compiled circuit into the FPGA chip. Test the functionalit of the circuit b toggling the switches and observing the LEDs. Part III The DE2 board provides 8 toggle switches, called SW 7, that can be used as inputs to a circuit, and 8 red lights, called LEDR 7, that can be used to displa output values. Figure 4 shows a simple Verilog module that uses these switches and shows their states on the LEDs. Since there are 8 switches and lights it is convenient to represent them as vectors in the Verilog code, as shown. We have used a single assignment statement LEDR = SW for all 8 LEDR outputs, which is equivalent to the 8 individual assignments assign LEDR[7] = SW[7]; assign LEDR[6] = SW[6];... assign LEDR[] = SW[]; To use SW 7 and LEDR 7 it is necessar to include in our Quartus II project the correct pin assignments, as we did for the pins used in Part II. Although we could enter these pin assignments manuall (8 for the switches plus 8 for the lights), a more convenient wa to make the required pin assignments is to import into the Quartus II software a file called DE2 pin assignments.csv, which is provided b Altera. For our convenience this file is included in the starter kit. The procedure for making pin assignments b importing the.csv file are included in the tutorial in Appendi D of the tetbook on pages 89 and 89. It is important to realize that the pin assignments in the DE2 pin assignments.csv file are useful onl if the pin names given in this file are eactl the same as the port names used in our Verilog module. The.csv file uses the names SW[]... SW[7] and LEDR[]... LEDR[7] for the switches and lights, which is the reason we have used these names in Figure 4. // Simple module that connects the SW switches to the LEDR lights module part (SW, LEDR); input [7:] SW; // toggle switches output [7:] LEDR; // red LEDs assign LEDR = SW; endmodule 4
Figure 4. Verilog code that uses the DE2 board switches and lights. Perform the following steps.. The project for this part is provided in the starter kit. Open the project named part.qpf in the part subdirector to begin our work. 2. Create a Verilog module called part for the code in Figure 4 and include it in our project.. Include in our project the required pin assignments for the DE2 board, as discussed above. Compile the project. 4. Download the compiled circuit into the FPGA chip. Test the functionalit of the circuit b toggling the switches and observing the LEDs. Part IV Figure 5a shows a sum-of-products circuit that implements a 2-to- multipleer with a select input s. If s = the multipleer s output m is equal to the input, and if s = the output is equal to. Part b of the figure gives a truth table for this multipleer, and part c shows its circuit smbol. s m a) Circuit s m s m b) Truth table c) Smbol Figure 5. A 2-to- multipleer. The multipleer can be described b the following Verilog statement: assign m = ( s & ) (s & ); You are to write a Verilog module that includes eight assignment statements like the one shown above to describe the circuit given in Figure 6a. This circuit has two eight-bit inputs, X and Y, and produces the eight-bit output M. If s = then M = X, while if s = then M = Y. We refer to this circuit as an eight-bit wide 2-to- multipleer. It has the circuit smbol shown in Figure 6b, in which X, Y, and M are depicted as eight-bit wires. Perform the steps shown below. 5
s 7 7 m 7 6 6 m 6 s X Y 8 8 8 M m a) Circuit b) Smbol Figure 6. An eight-bit wide 2-to- multipleer.. The project for this part is provided in the starter kit. Open the project named part4.qpf in the part4 subdirector to begin our work. 2. Include our Verilog file for the eight-bit wide 2-to- multipleer in our project. Use switch SW 7 on the DE2 board as the s input, switches SW 7 as the X input and SW 5 8 as the Y input. Connect the SW switches to the red lights LEDR and connect the output M to the green lights on the DE2 board, called LEDG 7.. Include in our project the required pin assignments for the DE2 board. As discussed in Parts II and III, these assignments ensure that the input ports of our Verilog code will use the pins on the Cclone II FPGA that are connected to the SW switches, and the output ports of our Verilog code will use the FPGA pins connected to the LEDR and LEDG lights. You can use the DE2 pin assignments.csv file to import the needed pin assignments. 4. Compile the project. 5. Download the compiled circuit into the FPGA chip. Test the functionalit of the eight-bit wide 2-to- multipleer b toggling the switches and observing the LEDs. Part V In Figure 5 we showed a 2-to- multipleer that selects between the two inputs and. For this part consider a circuit in which the output m has to be selected from five inputs u, v, w,, and. Part a of Figure 7 shows how we can build the required 5-to- multipleer b using four 2-to- multipleers. The circuit uses a -bit select input s 2 s s and implements the truth table shown in Figure 7b. A circuit smbol for this multipleer is given in part c of the figure. Recall from Figure 6 that an eight-bit wide 2-to- multipleer can be built b using eight 2-to- multipleers. Figure 8 applies this concept to define a three-bit wide 5-to- multipleer. It contains three instances of the 5-to- multipleer circuit in Figure 7. 6
s 2 s s u v m w a) Circuit s 2 s s m u v w s 2 s s u v w m b) Truth table c) Smbol Figure 7. A 5-to- multipleer. s 2 s s U V W X M Y Figure 8. A three-bit wide 5-to- multipleer. Perform the following steps to implement the three-bit wide 5-to- multipleer. 7
. The project for this part is provided in the starter kit. Open the project named part5.qpf in the part5 subdirector to begin our work. 2. Create a Verilog module for the three-bit wide 5-to- multipleer. Connect its select inputs to switches SW 7 5, and use the remaining 5 switches on the Altera DE2 board (SW 4 ) to provide the five -bit inputs U through Y. Connect the SW switches to the red lights LEDR and connect the output M to the green lights LEDG 2.. Include in our project the required pin assignments for the DE2 board. Compile the project. 4. Download the compiled circuit into the FPGA chip. Test the functionalit of the three-bit wide 5-to- multipleer b toggling the switches and observing the LEDs. Ensure that each of the inputs U to Y can be properl selected as the output M. 8