Laboratory Exercise 2

Transcription

1 Laoratory Exercie Numer and Diplay Thi i an exercie in deigning cominational circuit that can perform inary-to-decimal numer converion and inary-coded-decimal (BCD) addition. Part I We wih to diplay on the 7-egment diplay HEX to HEX the value et y the witche SW. Let the value denoted y SW, SW 8, SW 7 and SW e diplayed on HEX, HEX, HEX and HEX, repectively. Your circuit hould e ale to diplay the digit from to 9, and hould treat the valuation to a don t-care.. Create a new project which will e ued to implement the deired circuit on the Altera DE-erie oard. The intent of thi exercie i to manually derive the logic function needed for the 7-egment diplay. You hould ue only imple Verilog aign tatement in your code and pecify each logic function a a Boolean expreion.. Write a Verilog file that provide the neceary functionality. Include thi file in your project and aign the pin on the FPGA to connect to the witche and 7-egment diplay, a indicated in the Uer Manual for the DE-erie oard. The procedure for making pin aignment i decried in the tutorial Quartu II Introduction uing Verilog Deign, which i availale on the DE-Serie Sytem CD and in the Univerity Program ection of Altera we ite.. Compile the project and download the compiled circuit into the FPGA chip.. Tet the functionality of your deign y toggling the witche and oerving the diplay. Part II You are to deign a circuit that convert a four-it inary numer V = v v v v into it two-digit decimal equivalent D = d d. Tale how the required output value. A partial deign of thi circuit i given in Figure. It include a comparator that check when the value of V i greater than 9, and ue the output of thi comparator in the control of the 7-egment diplay. You are to complete the deign of thi circuit y creating a Verilog module which include the comparator, multiplexer, and circuit A (do not include circuit B or the 7-egment decoder at thi point). Your Verilog module hould have the four-it input V, the four-it output M and the output z. The intent of thi exercie i to ue imple Verilog aign tatement to pecify the required logic function uing Boolean expreion. Your Verilog code hould not include any if-ele, cae, or imilar tatement. Binary value Decimal digit Tale. Binary-to-decimal converion value.

2 Perform the following tep:. Make a Quartu II project for your Verilog module.. Compile the circuit and ue functional imulation to verify the correct operation of your comparator, multiplexer, and circuit A.. Augment your Verilog code to include circuit B in Figure a well a the 7-egment decoder. Change the input and output of your code to ue witche SW on the DE-erie oard to repreent the inary numer V, and the diplay HEX and HEX to how the value of decimal digit d and d. Make ure to include in your project the required pin aignment for the DE-erie oard.. Recompile the project, and then download the circuit into the FPGA chip.. Tet your circuit y trying all poile value of V and oerving the output diplay. Comparator z d v m Circuit B 7 6 d v v m m 7-egment 7 decoder 6 v m Circuit A Figure : Partial deign of the inary-to-decimal converion circuit. Part III Figure a how a circuit for a full adder, which ha the input a,, and c i, and produce the output and. Part and f the figure how a circuit ymol and truth tale for the full adder, which produce the two-it inary um = a + + c i. Figure d how how four intance of thi full adder module can e ued to deign a circuit that add two four-it numer. Thi type of circuit i uually called a ripple-carry adder, ecaue of the way that the carry ignal are paed from one full adder to the next. Write Verilog code that implement thi circuit, a decried elow.

3 c i a c i a a) Full adder circuit ) Full adder ymol ac i a c a c a c a c in ut c) Full adder truth tale d) Four-it ripple-carry adder circuit Figure : A ripple-carry adder circuit.. Create a new Quartu II project for the adder circuit. Write a Verilog module for the full adder ucircuit and write a top-level Verilog module that intantiate four intance of thi full adder.. Ue witche SW 7 and SW to repreent the input A and B, repectively. Ue SW 8 for the carry-in c in of the adder. Connect the SW witche to their correponding red light LEDR, and connect the output of the adder, ut and S, to the green light LEDG.. Include the neceary pin aignment for the DE-erie oard, compile the circuit, and download it into the FPGA chip.. Tet your circuit y trying different value for numer A, B, and c in. Part IV In part II we dicued the converion of inary numer into decimal digit. It i ometime ueful to uild circuit that ue thi method of repreenting decimal numer, in which each decimal digit i repreented uing four it. Thi cheme i known a the inary coded decimal (BCD) repreentation. A an example, the decimal value 9 i encoded in BCD form a. You are to deign a circuit that add two BCD digit. The input to the circuit are BCD numer A and B, plu a carry-in, c in. The output hould e a two-digit BCD um S S. Note that the larget um that need to e handled y thi circuit i S S = = 9. Perform the tep given elow.. Create a new Quartu II project for your BCD adder. You hould ue the four-it adder circuit from part III to produce a four-it um and carry-out for the operation A + B. A circuit that convert thi five-it reult, which ha the maximum value 9, into two BCD digit S S can e deigned in a very imilar way a the inary-to-decimal converter from part II. Write your Verilog code uing imple aign tatement to pecify the required logic function do not ue other type of Verilog tatement uch a if-ele or cae tatement for thi part of the exercie.

4 . Ue witche SW 7 and SW for the input A and B, repectively, and ue SW 8 for the carry-in. Connect the SW witche to their correponding red light LEDR, and connect the four-it um and carryout produced y the operation A + B to the green light LEDG. Diplay the BCD value of A and B on the 7-egment diplay HEX6 and HEX, and diplay the reult S S on HEX and HEX.. Since your circuit handle only BCD digit, check for the cae when the input A or B i greater than nine. If thi occur, indicate an error y turning on the green light LEDG 8.. Include the neceary pin aignment for the DE-erie oard, compile the circuit, and download it into the FPGA chip.. Tet your circuit y trying different value for numer A, B, and c in. Part V Deign a circuit that can add two -digit BCD numer, A A and B B to produce the three-digit BCD um S S S. Ue two intance of your circuit from part IV to uild thi two-digit BCD adder. Perform the tep elow:. Ue witche SW 8 and SW 7 to repreent -digit BCD numer A A and B B, repectively. The value of A A hould e diplayed on the 7-egment diplay HEX7 and HEX6, while B B hould e on HEX and HEX. Diplay the BCD um, S S S, on the 7-egment diplay HEX, HEX and HEX.. Make the neceary pin aignment and compile the circuit.. Download the circuit into the FPGA chip, and tet it operation. Part VI In part V you created Verilog code for a two-digit BCD adder y uing two intance of the Verilog code for a one-digit BCD adder from part IV. A different approach for decriing the two-digit BCD adder in Verilog code i to pecify an algorithm like the one repreented y the following peudo-code: T = A + B if (T > 9) then Z = ; c = ; ele 6 Z = ; 7 c = ; 8 end if 9 S = T Z T = A + B + c if (T > 9) then Z = ; c = ; ele Z = ; 6 c = ; 7 end if 8 S = T Z 9 S = c

5 It i reaonaly traightforward to ee what circuit could e ued to implement thi peudo-code. Line, 9,, and 8 repreent adder, line -8 and -7 correpond to multiplexer, and teting for the condition T > 9 and T > 9 require comparator. You are to write Verilog code that correpond to thi peudo-code. Note that you can perform addition operation in your Verilog code intead of the utraction hown in line 9 and 8. The intent of thi part of the exercie i to examine the effect of relying more on the Verilog compiler to deign the circuit y uing if-ele tatement along with the Verilog > and + operator. Perform the following tep:. Create a new Quartu II project for your Verilog code. Ue the ame witche, light, and diplay a in part V. Compile your circuit.. Ue the Quartu II RTL Viewer tool to examine the circuit produced y compiling your Verilog code. Compare the circuit to the one you deigned in Part V.. Download your circuit onto the DE-erie oard and tet it y trying different value for numer A A and B B. Part VII Deign a cominational circuit that convert a 6-it inary numer into a -digit decimal numer repreented in the BCD form. Ue witche SW to input the inary numer and 7-egment diplay HEX and HEX to diplay the decimal numer. Implement your circuit on the DE-erie oard and demontrate it functionality. Copyright c Altera Corporation.