Electron detector(s) decision to proceed with 2 detectors

Similar documents
Detector R&D at the LCFI Collaboration

Update: Lambda project

Electronics on the detector Mechanical constraints: Fixing the module on the PM base.

Integrated CMOS sensor technologies for the CLIC tracker

The LHCb upgrade. Outline: Present LHCb detector and trigger LHCb upgrade main drivers Overview of the sub-detector modifications Conclusions

Beam test measurements of the Belle II vertex detector modules

Towards Gfps CMOS image sensors. Renato Turchetta Barcelona, Spain

Work in Tbilisi. David Mchedlishvili (SMART EDM_lab of TSU) GGSWBS , Tbilisi. Shota Rustaveli National Science Foundation

Testing Gated Mode on Hybrid 4.1

Datasheet ADVAPIX TPX3. Version Datasheet. Model No.: APXMD3-Xxx170704

LHC Detector Upgrades

The Silicon Vertex Detector of the Belle II Experiment

The Phase-2 ATLAS ITk Pixel Upgrade

Construction of the Phase I upgrade of the CMS pixel detector

CMS FPGA Based Tracklet Approach for L1 Track Finding

Expected feedback from 3D for SLHC Introduction. LHC 14 TeV pp collider at CERN start summer 2008

The Belle Silicon Vertex Detector. T. Tsuboyama (KEK) 6 Dec Workshop New Hadrons with Various Flavors 6 7 Dec Nagoya Univ.

arxiv:physics/ v1 [physics.ins-det] 18 Dec 1998

SoLID GEM Detectors in US

Development of LYSO Detector Modules for an EDM Polarimeter at COSY. for the JEDI Collaboration

First Operational Experience from the LHCb Silicon Tracker

Track reconstruction for the Mu3e experiment based on a novel Multiple Scattering fit Alexandr Kozlinskiy (Mainz, KPH) for the Mu3e collaboration

Detector Control LHC

SVT detector Electronics Status

GLAST Silicon Microstrip Tracker Status

SoLID GEM Detectors in US

Validation of the front-end electronics and firmware for LHCb vertex locator.

Activity on GEM by the Rome group since last meeting

Velo readout board RB3. Common L1 board (ROB)

Simulation Study for EUDET Pixel Beam Telescope using ILC Software

Investigation of Proton Induced Radiation Effects in 0.15 µm Antifuse FPGA

The new detector readout system for the ATLAS experiment

Data Acquisition in Particle Physics Experiments. Ing. Giuseppe De Robertis INFN Sez. Di Bari

Endcap Modules for the ATLAS SemiConductor Tracker

The Silicon Tracking System: Mechanical Integration and Alignement

All Programmable SoC based on FPGA for IoT. Maria Liz Crespo ICTP MLAB

CMS Strip Tracker R&D

Design Status of the CERN-SRAM macrocell

FLAME, a new readout ASIC for the LumiCal detector

Alternative Front-End Electronics (for LBNE & PET) Kurtis Nishimura University of Hawaii LAPPD Collaboration Review December 8, 2011

L. Pina, A. Fojtik, R. Havlikova, A. Jancarek, S.Palinek, M. Vrbova

High Rate Diamond Detectors for Heavy Ions. ultra thin detectors for REX-ISOLDE. tracking detectors for R3B

The performance of the ATLAS Inner Detector Trigger Algorithms in pp collisions at the LHC

Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

Quad Module Hybrid Development for the ATLAS Pixel Layer Upgrade

EUDET Telescope Geometry and Resolution Studies

Interpolating Silicon Photomultipliers

Extremely Fast Detector for 511 kev Gamma

Simulation study for the EUDET pixel beam telescope

TOF Electronics. J. Schambach University of Texas Review, BNL, 2 Aug 2007

Streaming Readout, the JLab perspective. Graham Heyes Data Acquisition Support Group Jefferson Lab

Readout Systems. Liquid Argon TPC Analog multiplexed ASICs SiPM arrays. CAEN 2016 / 2017 Product Catalog

XDAS-V3 1.6 mm pitch dual energy X-ray data acquisition system

Development of a high resolution animal PET with continuous crystals and SiPMs

Recent R&D Results on a Pixel Detector for Belle. Gary S. Varner University of Hawai, i SVD Upgrades October 23, 2000

Burn-In Software Development. Taras Fedorchuk, Taras Shevchenko National University of Kyiv 3rd September 2018

APV-25 based readout electronics for the SBS front GEM Tracker

PSEC-4: Review of Architecture, etc. Eric Oberla 27-oct-2012

SYNCERITY TM 1024 x 256

Overview of SVT DAQ Upgrades. Per Hansson Ryan Herbst Benjamin Reese

The Application of DAQ-Middleware to the J-PARC E16 Experiment

LINX linear X-ray sensor data sheet V3 type

Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

Straw Detectors for the Large Hadron Collider. Dirk Wiedner

TEST, QUALIFICATION AND ELECTRONICS INTEGRATION OF THE ALICE SILICON PIXEL DETECTOR MODULES

Loma Linda University Medical Center Dept. of Radiation Medicine

ALIBAVA: A portable readout system for silicon microstrip sensors

3D Integration & Packaging Challenges with through-silicon-vias (TSV)

Space Radiation and Plasma Environment Monitoring Workshop 13 and 14 May ESTEC. Efacec Space Radiation Monitors MFS & BERM

High speed CMOS image sensors Wim Wuyts Sr. Staff Applications Engineer Cypress Semiconductor Corporation Belgium Vision 2006

Performance of FPCCD vertex detector. T. Nagamine Tohoku University Feb 6, 2007 ACFA 9, IHEP,Beijin

AIDA Advanced European Infrastructures for Detectors at Accelerators. Presentation

Update on PRad GEMs, Readout Electronics & DAQ

ATMEL ATF280E Rad Hard SRAM Based FPGA. Bernard BANCELIN ATMEL Nantes SAS, Aerospace Business Unit

Trigger Layout and Responsibilities

HPS128-LT-S Hybrid pyroelectric linear array with 128 responsive elements and integrated CMOS multiplexer

TORCH: A large-area detector for precision time-of-flight measurements at LHCb

Optimization of thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC arxiv: v1 [physics.ins-det] 12 Jan 2017

Results of a Sliced System Test for the ATLAS End-cap Muon Level-1 Trigger

Detector Housing CASCADE-U 100. Bottom-flange. Top-flange with Teflon insulating ring and special Wilson-flange designed to fit the UCN beam pipe

Delayline Detectors. Imaging Detection of Electrons, Ions & Photons with Picosecond Time Resolution. e - I +

What s New in Data Acquisition

Both equations are solved using a finite differences (iterative relaxation) method, which takes some time to converge.

DAQ & Control with PXI. Murali Ravindran Senior Product Manager

INFN Padova INFN & University Milano

The ASDEX Upgrade UTDC and DIO cards - A family of PCI/cPCI devices for Real-Time DAQ under Solaris

Enhancing the Detector for Advanced Neutron Capture Experiments

FT Cal and FT Hodo DAQ and Trigger

Time and position resolution of high granularity, high counting rate MRPC for the inner zone of the CBM-TOF wall

DSP BASED MEASURING LINE-SCAN CCD CAMERA

Front end electronics and system design for the NUSTAR experiments at the FAIR facility. FEE 2006 Workshop

DC140 1 GHz 2 GS/s DC GHz 1 GS/s. Ctrl I/O. Dual-Channel 3U PXI/CompactPCI High-Speed Digitizers

NEMbox / NIMbox Programmable NIM Module

GSI Event-driven TDC with 4 Channels GET4. Harald Deppe, EE-ASIC Holger Flemming, EE-ASIC. Holger Flemming

Signal Conversion in a Modular Open Standard Form Factor. CASPER Workshop August 2017 Saeed Karamooz, VadaTech

Full 3D scan of an AGATA crystal using the PSCS technique

The FTK to Level-2 Interface Card (FLIC)

Development of scalable electronics for the TORCH time-of-flight detector

FPGA based charge fast histogramming for GEM detector

MSU/NSCL May CoBo Module. Specifications Version 1.0. Nathan USHER

Transcription:

Electron detector(s) decision to proceed with 2 detectors Direct hit detector (DH1K) reciprocal space Fast application (DH80K) real space imaging Thin nonlinear DEPFETs Thin (nonlinear) Fast DEPFETs Thin detector (20-50 µm) ~ 1000 Hz full frame rate Primary electrons 60-300 kev and 1-5 MeV 1E 5-1E 8 electrons within < 1ps, (1000 Hz rep. Rate) Thickness of detector (20-50 µm) 80 khz +/- full frame rate Primary electrons 100-300 kev 1E 8 electrons within < 10ns, (80 khz rep. Rate) Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 1

Electron Detector DAQ Overview Direct Hit (DH1k) and ultra fast detector DH80k need different read-out due to their different frame rates: Direct Hit (DH1k) DH80k Frame Rate 1 khz 80 khz Data Stream Continuously Burst with 100 frames Read-out DCDEMCv1 + FPGA or DCDEMCv2 +DEPFET Movie chip DCDB? + DEPFET Movie Chip Pixel arrangement 512 x 512 2 fold readout 512 x 512 4-fold readout ADC resolution 8 bit? 8 bit Image type Momentum space image Real space image (additional pixels for Common Mode correction needed) Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 2

Electron detectors: simulation Sensor definition ongoing. Initial thickness studies done (Florian). PhD student took over. Required information: backscattering from the material behind the sensor 300 kev electrons Lateral RMS (straggling) [ Mikrometer] 80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00 300 kev 500 kev 0 50 100 150 Thickness of Silicon [Mikron] 450 µm thick Silicon 50 µm thick Silicon Question to Sasha: How much material (Si) can we afford to have behind the detector What is optimal thickness of the sensor with 60um pixel size Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 3

Electron detectors: Sensor Status DH1K Conceptual design of sensors done - basic cell defined and simulated nonlinear DEPFETs require new ASIC developments collaborative effort with external groups DCDEMC (I. Peric) Wafer layout: 4 x 512 pixels Test structures 60 µm pitch, two fold read out nonlinear DEPFETs 4 x 512x512 modules (1Mpixel) Radiation hardness / still optimizations To be done to start sensor production: Definition of sensor thickness Matrix layout Periphery layout Start SOI production by 1.06.14 Start DEPFET processing by 1.10.14 8-10 wafers for 512? Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 4

Modular HLL DAQ System - A dedicated board (IGELlight) is used for all communication tasks - The I/O synchronization Board is used for data acquisition and trigger processing - The modular design allows the separation of different task to different FPGA firmware packages (easier to maintain the firmware versions) - The prototype of the IGELlight board is already tested - The I/O board is currently being developed I/O Board IGELlight Board Smallest unit: 1 x I/O Board, 1x IGELlight board Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 5

Direct Hit Detector DH1k 30mm 4 x DCDEMC (with 256 inputs) 8 x Switcher (with 32 Gate and Clear channel each) Decision on the two options: DCDEMCv1 +FPGA DCDEMCv2 +DMC - 4 slots used for I/O and communication boards - DAQ system includes trigger and time-stamping of the data - Easily scalable by adding IO and communication boards Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 6

Direct Hit Detector DH1k 512 x512 pixel Large Direct Hit detector would need 2 compactpci racks with 16 I/O and communication boards Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 7

Direct hit detector DH80K Sensor: use Belle-like DEPFET layout with 60 µm pixel size, and read out from both sides 1024x1024 pixels (bidirectional 4-fold readout) Radiation hardness of the detector to be defined 1Mpix, 60μm DEPFET pixel, 4 quadrants, 6x6 cm² sensitive 20-50μm thin sensitive area Bidirectional 4-fold read out frame rate: 100ns 500/4 pixel = 12.5μs 80kHz DCDB? + DMC (with memory to store 100 frames) Windowed mode operation? Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 8

Direct Hit Detector FDH80k 512 x512 pixel Question to Sasha: Can we allow to have some dead space How much? 60mm SOI production together with DH1k Start DEPFET processing by 1.01.15? 8 or 10 wafers? Edet HLL Internal meeting 11 April 2014 Jelena Ninkovic 9