Built-in i Repair Analysis 2010. 10. 20 Woosik.jeong@hynix.com

Contents 1. RA 2. BIRA 3. Previous Works 4. Summary 1/ 38

1. RA 2. BIRA 3. Previous Works 4. Summary 2/ 38

Repair What is Repair? Replacing a faulty cell with a healthy redundant cell 3/ 38

RA (Redundancy Analysis) What is RA (Redundancy Analysis)? Finding ng address information on to be repaired for each spare line Column address C1: 4 C2: 5 R1: 3 Row address R2: - 4/ 38

Spare Architecture (1) Bit spare architecture -PPR R( (Post Package Repair) 5/ 38

Spare Architecture (2) 1D line spare architecture -Some simple SoC 6/ 38

Spare Architecture (3) 2D line spare architecture -Most of hgh high density memories - Difficult RA 7/ 38

Fault Classification Three types of faults R S (C S ): # of row (column) spares. k: # of repetitive faults on a line. 8/ 38

Observations on RA Observation 1 A single fault can be replaced with either a spare row or spare column. Observation 2 A sparse faulty row (column) line can be replaced with a spare row (column). However, it can also be replaced with several spare columns (rows) according to the number of available spares. Observation 3 A must-repair faulty row (column) must be replaced with a spare row (column) line. 9/ 38

RA Classification Three types of RA -Fault storing space 10 / 38

RA Example R0 R1 C0 C1 Faulty cell 2 Row spare lines 0 1 2 3 4 5 6 7 R0 R1 0 1 2 3 4 5 6 7 C0 C1 X X X X X X X X 2 Column spare lines Repair solution Failure bitmap 11 / 38

RA Example 0 R0 1 1 X X 2 X 3 X X R1 3 4 X 5 C0 4 6 7 C1 6 R0 R1 0 1 2 3 4 5 6 7 C0 C1 X X Repair solution Failure bitmap 12 / 38

1. RA 2. BIRA 3. Previous Works 4. Summary 13 / 38

BIRA vs. BISR BIRA: Built-in Repair Analysis (b, c) BISR: Built-in Self Repair = BIRA (b, c) + Soft repair (d) 14 / 38

History RA algorithm RM(1984), B&B (1986) BIRA Cresta (2000) LRM, ESP, LO (2003) IntellignetSolve (2007) SFCC (2009) BRANCH (2010) 15 / 38

Key Features of BIRA Area Overhead Repair Rate Analysis Time Good Bad ESP, LRM CRESTA Intelligent SolveFirst 16 / 38

Classification by features Non-optimal Repair Rate Optimal Low Area Overhead Parallel Analyzer Single Analyzer ESP CRESTA Intelligent SolveFirst SFCC BRANCH Low area High area LRM Low area High analysis speed Middle area 17 / 38

Repair Rate Optimal repair rate = 100% of normalized repair rate = Always find solutions if exists 18 / 38

RA for single (sparse) Fault Single fault Can be repaired by either a row or a column Requires at least one spare line spares Repairble if # of single faults # of available Repairable if # of Maximum sparse faults = 2*R S *C S Where, R (C) is # of row (column) spares 19 / 38

RA for Must-repair Must-repair Do not need to be analyzed Requires one spare line # of must-repair # of available spares (# of single faults + # of must-repair) # of available spares 20 / 38

Binary Search Tree # of branches in a tree = (R S+C S)! /(R S!*C S!) = (2+4)!/(2!*4!) = 15 where, RS: # of rows CS: # of columns # of nodes in a branch = (R S +C S ) = (2+4) = 6 branch node 21 / 38

1. RA 2. BIRA 3. Previous Works 4. Summary 22 / 38

RM (Repair Most [1984]) Fast but, Non-optimal repair efficiency. i Not searching all cases. 23 / 38

LRM (Local Repair Most [2003]) Local bitmap scheme. The size of bitmap depend on the defect distribution. Non optimal repair efficiency 24 / 38

ESP (Essential Spare Pivoting) Non optimal repair efficiency but smallest area overhead During test sequences running After finishing test sequences Fail address From BIST Fail address comparing and orthogonal address saving Post RA processing block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 C0 C1 time 1 1 3 3 2 7 6 7 1 5 3 5 2 9 9 9 Orthogo onal addr ress 구분 Orthogonal address 1 1 3 3 2 7 9 9 Essential flag 1 0 1 0 1 1 0 1 (a) fail address save area End of RA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 R0 R1 X X X X X X X X Orthogonal address : address has different x, y address against previous orthogonal addresses first address is orthogonal address 25 / 38

CRESTA (Comprehensive Real-time Exhaustive Search Test and Analysis) Implementation the entire searching tree Optimal repair rate & fast High area overhead 26 / 38

How to RA on CRESTA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 R0 R1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 C0 C1 Fault Row Col. 1 st 1 1 X X X X 2 nd 3 3 X X 3 rd 2 7 X 4 th 6 7 5 th 1 5 X 6 th 3 5 7 th 2 9 8 th 9 9 < Policy > 1. Compare with prelogged address 2. If there is no same address then update new address else skip. 3. If there is no more spaces to log, it is not a correct solution. R0 1 R0 1 R0 1 C0 1 C0 1 C0 1 R1 3 C0 3 C0 3 R0 3 R0 3 C1 3 C0 7 R1 2 C1 7 R1 2 C1 7 R0 2 C1 9 C1 7 R1 3 C1 7 R1 1 R1 6 Sub-analyzer #1 Sub-analyzer #2 Sub-analyzer #3 Sub-analyzer #4 Sub-analyzer #5 Sub-analyzer #6 27 / 38

IntelligentSolve(First) Single RA analyzer Sequential analysis (node by node) with must-repair skip Optimal repair rate Not fast 28 / 38

SFCC (Selected Fail Count Comparison) Building binary search tree based on line faults must-repair skip Analyze by comparison of fail count of lines Optimal repair rate and fast 29 / 38

SFCC 1) Repairable if (SFC >= (TFC- unused line counts)), 2) Repairable if (SFCR >= (TFC- unused line counts)), where, TFC : total fail count of sparse faults SFC : sum of fail counts of most-fails SFCR : SFC interchanging fail count each other 30 / 38

BRANCH Single RA analyzer Based on ESP but optimal repair rate Comaparing Parent (Orthogonal) vs. Child (non-orthogonal) Analyze Faster (parallel comparison of all nodes in a branch) 31 / 38

BRANCH 32 / 38

Result area (fault saving area calculation only) Area [# of bits] 3000 2500 2000 1500 1000 CRESTA LRM ESP INTEL SFCC BRANCH 500 0 1 2 3 4 5 6 7 8 9 10 11 Column spares (Cs) 33 / 38

Result area (fault saving area calculation only) Area [# of bits] 20000 19000 18000 17000 3000 2500 2000 1500 1000 CRESTA LRM ESP INTEL SFCC BRANCH 500 0 64x64 128x128 256x256 512x512 1024x1024 2048x2048 Memory size [MxN] 34 / 38

No ormalized Repair rate 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 Result Repair rate CRESTA RM (LRM max.) ESP INTEL SFCC BRANCH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Random faults [ea] 35 / 38

Result Analysis Speed 1200 1100 Clock cycles 1000 RM (LRM max) 900 INTEL SFCC 800 BRANCH 700 600 500 400 300 200 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Random faults [ea] 36 / 38

Result Overall Performance ecution cycles 200 IntelligentSolveFirst 180 160 140 120 100 RA exe 80 60 40 20 0 SFCC BRANCH Ideal BIRA 5 10 Storage requireme ments 15 20 25 30 2.5% 3.0% 2.0% 15% 1.5% CRESTA 1.0% 0.5% 35 00% 0.0% Rate of Over-useded Spares 37 / 38

Summary Complexity of RA depends on Spare architecture t and #of spares Area overhead depends on Spare architecture, #of spares and kind of BIRA To achieve optimal repair rate, All sparse faults must be stored by using single RA analyzer To enhance analysis speed, reducing binary search tree, parallel operation, etc. 38 / 38