BIST is the technique of designing additional hardware and software. features into integrated circuits to allow them to perform self testing, i.e.

Transcription

1 CHAPTER 6 FINITE STATE MACHINE BASED BUILT IN SELF TEST AND DIAGNOSIS 5.1 Introduction BIST is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self testing, i.e., testing of their own operation using its own circuits, thereby reducing the dependency on an external automatic test equipment. BIST is a design for testability technique as it makes the electrical testing of a chip easier, faster, cheaper and more efficient. The issues need to be considered when implementing a BIST are i) faults to be covered by the BIST and how to test them, ii) Chip area occupied by the BIST circuit and iii) External supply and excitation requirements of the BIST. The use of memory core in SOC designs is rising quickly. Today the on chip memory cores occupy more than 60% of the area of a SOC. Normally, the dense memory core is more prone to faults. Hence, there is a need to design a memory BIST for the complex SOCs. To reduce the test time and cost two different MBIST design approaches are presented in this thesis. The issue of devising efficient methods for the diagnosis of embedded memories is becoming of increasing importance [14]. To facilitate the effectiveness of repair, the overall defect level should be kept under

2 control and requires the ability to deeply analyze the root cause of faults. Hence, an efficient diagnosis solution is required [16]. The present chapter deals with the hard wired FSM based MBIST design. It adds a custom circuitry to each core, implementing a suitable BIST algorithm [lo]. The main advantage of this approach is test application time in short and the area over head is relatively small compared to programmable MBIST. It consists of a circuit implementing a suitable BIST algorithm (March C Test algorithm) and the design provides a diagnostic capability to have exact knowledge of fault address and number of faults in a word oriented memory. 6.2 Memory BIST An MBIST unit consists of a controller to control the flow to test the sequence and other components to control the necessary test control and data. Design of MBIST controller can be classified into three types i.e. i) hard wired, ii) Micro Code base and iii) Processor base. A hard wired controller is an FSM, a hardware realization of a selected memory test algorithm. Classical memory test algorithm like zero-one, checker board are either simple, and walking, GALPAT, sliding diagonals etc., are fast but have poor fault coverage, or have a good fault coverage but with complexity and slow test process. Where as MARCH test are universauy employed memory test to test wide range of fault models like SAF, CF, TF, and AF faults. A March based algorithm is a finite sequence of March elements. Since March based tests are simple and can provide

3 good fault coverage, they are dominant test algorithm implemented in most of the MBISTs. Consider the 9N MARCH test shown in table 5.1 to illustrate the typical MARCH test. 9N March 00 (wo); h(r0wl); h(rlw0); U(r0wl) U(rlw0) /----Retention Test-----/ March wt 10 11wt 12 Add& wo ro wl rl wo ro wl rl wo ro wl rl Addrl wo ro wl rl wo t t t t r0 wl rl Table 6.1: 9N MARCH TEST The Table 5.1 shows a bit oriented 9N MARCH test algorithm as an example consisting of 5 March elements. In each element, first it specifies the address sequence fl means the address sequence is in ascending order, means the address sequence is in descending order, and means either ascending or descending is acceptable. For example consider March element 1, the address sequence begins at the lowest address and changes in ascending order. For each address the

4 algorithm performs a read operation with an expected Zero and writes back the complemented bit immediately and continues to the next address. The algorithm is called March 9N test algorithm as it contains 9N readlwrite operations, where N is the number of memory cells, and the retention test is for DRAMS. For multi bit word memories, those with dimensions 2' rows by 2c columns by b-bits, the March test must be performed log (b) + 1 times in order to detect coupling faults within a word. Half of the background patterns necessary to test multi bit words with a March test are shown for 8 bit and 32 bit words in the table 5.2 and 5.3. The other half of the necessary patterns are the inverse of these listed. Table 6.2: Word pattern for 8 bits.

5 Table 5.3: Word pattern for 32 bits. Apart from self testing, designing an efficient approach to diagnose an embedded memory is gaining importance. To allow improvements in the production process, exact knowledge about the memory cells affected by the faults and the type of faults is required. This is what is implemented as BIST and BISD architecture to test and diagnose the SRAM. 5.3 MBIST architecture The proposed MBIST runs a test sequence which implements a March C algorithm. The March C algorithm is suitable for testing AF, TF, SAF, CF at the RAM cell array. It has the highest coverage of physical spot defects among other marching algorithms. The March algorithm consists of 6 marching elements denoted as (MI, M2, M3, M4, M5, and M6) = ffu (~0); fi(i-0~1); fl(rlw0); U(r0wl) U(rlw0) U(I-0). In case of word oriented RAMS several cells of RAM are simultaneously being written then the CF within the cells of a word are tested by back pattern generating unit to generate the patterns as shown in the Table 5.2 and Table 5.3. The

6 architecture of MBIST has been designed to support self testing and diagnosis with the design and testability goals as follows: The BIST design must be as independent as possible of the size of the embedded RAM. r The embedded RAM should be tested and diagnosed for the SAF, TF, CF, and AF fault models. r To maintain a minimal area overhead * However the effects of multiple faults are not considered Given the above design constraints, different design choices concerning to the BIST architecture are adopted. r The Single Port memory including the decoding logic. The data path consisting of all registers, Counters, Multiplexes, Comparator and random logic around the memory. The BIST controller i.e. the FSM based controller is responsible for generating the correct sequence of operations composing the test algorithm. 0 The BISD controller to diagnose the memory and generate the fail map.

7 A typical embedded memory BIST comprises of an MBIST wrapper, a MBIST controller and the inter connections between them as shown in Figure 5.1. Figure 5.1: MBIST Architecture The MBIST wrapper further includes an address generator to provide complete memory address sequences, a Background Pattern Generator (BPG) to produce the data patterns when testing word-oriented memories, a comparator (Compare) to check the memory out put against the expected correct data pattern, and a FSM to generate proper test control signals based on the commands received from the MBIST controller. The FSM performs the March, through up/down counter to generate address, a data generator, and minimal control circuitry to control the memory enable signals. The MBIST controller pre- process

8 the commands received from the upper level controller (either on-chip microprocessor or off-chip ATE) and then send them to the MBIST wrapper. The interconnection between the wrapper and the controller could be either serial (i.e., a single command line is shared by the wrapper) or parallel (i.e., dedicated multiple command lines are linking different wrappers to the controller). Figure 6.2: A Generic State Diagram of the FSM based MBIST The main steps for running MBIST as shown in figure 5.2 are: 1. When the Test mode signal is asserted, the BIST controller starts running memory test. The test mode signal must be asserted until the controller completes the test and asserts the test End signal.

9 88 2. For each test session, the controller generates the conm I sip& to the upldown counter, readlwrite logic and pattern generators logic depending on the March element to be run. 3. After the controller commands the above logic, it monitors the response data by shifting the data out to the comparator logic. If a fault is detected, the error signal is asserted by the controller to report the error status. 4. The error signal acts as an initialization signal to the BISD unit. 5. If no error is found, by the present march element the controller switches to the next state and repeats the commands till the test session is finished. 6. With each fault detection signal from the BIST process, the BISD unit collects the fault information like address, fail map and the count of faults. 7. After completing the last test state without any fault, the BIST end signal is asserted to denote that the memory under test have passed the test and test-mode signal may be de-asserted if no fault is detected, else asserts the ERROR signal 8.4 BISD Architecture The top level architecture of the proposed BISD consists of BIST controller, BISD controller, memory under test and external stimuli, usually a microprocessor which accesses the memory under test. Here

10 BIST and BISD are treated as one module and they go together in this architecture. However, additional circuit components like multiplexers are used to channel the signals like read, write, data in, data out, address coming from the microprocessor (externally) and from the BIST controller internal to the chip), depending on the mode. In test mode the output from the memory array i.e., data out will be given to the de- multiplexer which gets distributed to two signals, of which one signal will be going to the comparator to detect the presence of errors, while the other signal is the output of the memory under normal mode. The presencelabsence of error is indicated using the output signal 'ERROR'. Whenever, an error is detected by the BIST in a memory location, immediately the fail map and the corresponding memory address will be stored for the self repair process BISD Implementation The proposed BISD block consists of three sub-blocks viz; BIST controller for fault detection, BISD controller for the diagnosis and a set of registers to store the fail maps and their corresponding addresses for fault diagnosis. Fail map is nothing but the bitmap of the faulty word of the memory under test. For example, if ' " is the expected data from a memory location and " " is the dak read from that memory location due to certain fault, and then the fail map is generated

11 ,. J,>{ dnb Y by logically ex-oring the expected data and the read data, resul the fail bit data, i.e., " " for this example. As mentioned earlier, the BIST controller is based on a finite state machine, each state representing one of these March elements. The algorithm can be implemented using seven state transitions (including initial state) as shown in figure5.3 In each of the states (except the initial state) either a 'read' operation or a 'write' operation or a combination of both will be taking place. However, word oriented memories should be checked for coupling faults. Hence, the number of states is increased to thirteen viz: states SC1 to SC7 for coupling faults and S1 to 56 for the remaining faults. In each of those additional states, a set of patterns shown in table 5.2 and table 5.3, are written and read from the memory cells. To Start with, any BIST controller designed using March test procedures stays in the initial state, as and when the specified conditions are met, the state transition begins. Depending on the March algorithm, a particular March element runs through the entire memory array either in incrementing or in decrementing fashion.

12 When Modes '0' When reset *'01 When Mode= 'I' Address = 'max' Address '0' a / \ I I d Address = '0' \ ~ddress ='max9 ' Address = 'max' Address '0' Figure 5.3: State diagram for March C algorithm BIST Controller Implementation BIST controller is implemented as a FSM, which makes use of March C algorithm, explained in Basically for the implementation it is considered as five processes, among which three are sequential and two are combinational in nature. Each of the process deals with one unit of the BIST architecture. The processes are explained below. a Process 1 deals with the reset logic. The machine stays in initial state until the reset and the test mode signals are enabled. i.e., when the reset and mode signals are active high, it changes its state.

13 Rocess 2 deals with state change logic. Depending upon the March elements, for every rising edge of the clock, the state changes if the conditions shown are met. Process 3 deals with the counter logic. It generates a complete set of addresses for the memory under test either in increasing or decreasing Process 4 deals with test pattern generation logic. It generates the test vectors specified by each March element in the corresponding state, depending on the signals control, read and write. Process 5 deals with the comparator logic. During memory 'read' cycle, the comparator checks the data from the memory against the correct response preloaded in the register using the signal 'data to comparator' to issue an error/no error signal Fault Diagnosis and Location The traditional March C algorithm is aimed at detecting the faults and it do not support implicit fault diagnosis and fault location. To efficiently address this problem, a March-based fault location algorithm has been proposed in this architecture. To accomplish this, a concurrent process runs along with BIST to store the failure information. A set of registers called 'Fail map Registers' are taken to store the failure information during the BIST. Each register is of two fields. The Most significant field bits represent the address field and the least significant field bits

14 represents the faulty bit information of the faulty row of the memory under test. As and when a fault is detected in the memory during BIST, the address of that memory location i.e,, row address will be stored in the first field and the corresponding fail map will be stored in the second field of the fail map registers. If the same location is subjected to a different fault at different instance during BIST, the second field bits will be updated with the new value and the address being the same. At the end of BIST, a set of faulty locations in the memory along with their corresponding fail maps will be available to aid for repairing those faulty locations. 5.8 Simulation and Synthesis report For the functional verification of the above proposed BISD architecture a memory block of sixteen words, each of one byte is used. Aldec Active HDL version 6.3 is used for simulation. The simulated code is synthesized using Xilinx ISE 8.2i Foundation Software, making use of the FPGA Spartan 3E.For higher memories ASIC tool 'Design Compiler' of Synopsis is used, targeted to 0.13micron technology with an operating frequency of 250MHz Simulation Reaults As mentioned earlier, the entire fault detection and diagnosis is performed using a FSM having thirteen states, each representing a

15 March C element. The following figures from figure 5.4 to 5.14 are the simulation results obtained for an SRAM of sixteen bytes. Reset logic When the reset signal (ramcontroller-rst-i) is low, the machine will be in its initial state (SO-init). As and when the reset signal is active high and the mode is test mode (ramcontroller-test-mode-i= '13 the machine gets started with a transition from initial state to the first state SC1 as shown in figure 5.4. The signal march-start-i is used to trigger the FSM, Figure5.5 shows the complete cycle of the state machine depicting the thirteen states. Figure 5.4: State transition from initial state 80-init to SC1 Figure 6.5: Thirteen rtater in the F W

16 Address Generation: Figure 5.6 shows the address increment in state S1. The March element in this state is {UfiwO}, i.e.; writing zero in all the sixteen memory locations, addresses of which are generated by the counter signal ramcontroller-count-o. Figure 5.6 Addretm Increment in 81 Fault induction in SC1: Figure5.7 shows how an error is simulated into the memory location. When the signal ramcontroller-cntl-i is low, an erroneous data of FF is written into the memory locations 06 and 07 instead of OF. Figure 6.7: Fault Induction in SC1

17 Fault detection in SC2: The faults in locations 06 and 07 are detected by the comparator during the 'read' (active low) operation in SC2 state as shown in the figure 5.8. The fail maps and the corresponding faulty addresses are also stored in fail map registers FMO and FM 1. Figure 5.8: Fault Detection in 8C2 Similarly, figures 5.9 and 5.10 show the fault simulation and detection in OE and OF memory locations in states SC3 and SC4 respectively.

18 Figure 5.9: Fault Induction in SC3 Figure 5.10: Fault Detection in SC4 The ramcontrollor~error~out signal in figure 5.11 indicates the fault in OE and OF memory locations. It is an output signal (active high) indicating whether the memory is faulty or erroneous.

19 Figure 5.11 Error output signal b State transition The March element in state S3 is {h(rl,w0) i.e., reading the data " " which was written in previous state (S2) and writing the data " " in all the memory locations in increasing order (00 to OF). The March element in state S4 is {U (r0,wl) i.e., reading the data " " which was written in previous state (S3) and writing the data ' " in all the memory locations in decreasing order (OF to 00). Figure 5.12 shows the state transition form 53 to S4 when the address is OF. Figure 5.12: State Transition from State 83 to state 84

20 Figure 5.13 shows the address decrementing in state S4 as the March element in this state is {U (ro, w 1). Figure 5.13: Address Decrement in 84 FSM Completion After all the March elements (all 13 states) are executed, the state machine returns to the initial state SO-initial with an indication by the march-done-o signal being high, shown in figure The fail maps shown in the figure 5.14 indicates that the memory under test consists of four faulty locations. Their addresses and the corresponding fail maps can also be seen. Figure 5.14: March C completion.',,/.:,-' i i ' t. _..- I---.-_,-.-., -.,':I, ,, :): oc\,' / ' \ /? I 11' I,,'. '.

21 5.5.2 Synthesis Results The simulated code is synthesized using Xilinx ISE 8.2i Foundation Software, making use of the FPGA Spartan 3E. For higher memories ASIC tool 'Design Compiler' of Synopsis tool is used, targeted to 0.13 micron technology with operating frequency of 250MHz. The following figures from figure 5.15 to figure 5.18 show the top level RTL schematics of the proposed BlSD design. Figure5.15: RTL Schematic top view of the proposed Memory BI8D

22 101 The internal views of the schematic are shown in the figures. 16 to Figure 5.16: Internal Block Schematic of the proposed BISTIBI8D

23 - Figure 5.17: Internal Schematic of B18T Controller

24 Flgurs 5.18 {a)

25 Figure 6.18 (b)

26 Figure 5.18: Internal Gate level Schematics of BIST Controlhr 5.6 Conclusions From the present FSM based BISTIBISD architecture design different parameters are analyzed which are discussed below.

27 Timing Report and gate count Comparison Table 5.4 shows the access time (Total testing time) and the gate count for different SRAM sizes. It shows a non-exponential increase in the access time as the size of memory increases. * Memory Sizes lk bytes 4k bytes 8k bytes 16k bytea 32k bytes 64k bytes Module B18T BIST BIST BIST BIST BIST Time 8.334ns 8.512ns 9,280ns ns no ns Gate Count Table 5.4: Comparison of Access Time and gate count

28 Memory Memory + BIST Aocsrr 8ke 8 8FF LUT IOB C 8 SFF LUT IOB C ' ~ P C (Bib) WORD 1024 Adblc unit8 in Spartan 3E 7 i F ~ ~ ~ ~ ' I! Table 6.5: Comparison of Device Utilization with and without BI8T S-Slices SFF-Slice Flip Flops LUT- Loo k-up Tables IOB- Input/ Output Blocks C-Clock Table 5.5 gives a detailed comparison on the device utilization in FPGA Spartan 3E, in terms of slices, slice flip flops, look-up tables, input/output blocks and clocks.

29 Memory Sizes l6bytes 4k bytes 32bytes 64k bytes Module MBIST MBlST MBlST MBIST (Access type Word Wise) Power ~~ ~~ ~~ 201.OYuw Area Over head mm mm mm mm Time ns ns ns ns Cell Count Table 5.6: Comparison of Access Times, Area overhead and Dynamic Power for BIST /BED using Design Compiler The gate count for different memory sizes is shown in the table 5.4. No significant increase in the area over head is observed. Table 5.6 gives the

30 cell counts, area overhead, power dissipation and time delay for different memory blocks. These are obtained from the Design Compiler tool. The figure 5.19 expresses the variation in power, area overhead, cell count and time delay for different memory sizes with the proposed BISTIBISD design. 1 C4*h*n.mM Po*.ffofBlsTml~ 1 Comp~rhion 61 YOI ovorho~d using Design Cornpilaw using Design Complkr I I I for BlSTiBlNI On*MofI*loCmmDu~ D*I. 1 Conparldon dqil Mkw WTfNSD udng Onpikr I i i Ikdgn Compiler Memory / I Figure 5.19: Overhead due to BIBT Circuitry for Merent Memory Sizes