Lecture 10: Simple Data Path Course so far Performance comparisons Amdahl s law ISA function & principles What do bits mean? Computer math Today Take QUIZ 6 over P&H.1-, before 11:59pm today How do computers execute instructions? From specification to state changes In order simple data path execution UTCS 352, Lecture 10 1 Exam Return Perusal in ACES 3.22 (Gem Naivar s office) Questions in office hours Grade distribution 90-100 2 80-89 19 70-79 29 60-69 16 50-59 3 - Go to office hours 0-9 1 30-39 2 0-29 0 UTCS 352, Lecture 10 2 1
ISA Specifies How the Computer Changes State formats types ressing modes instruction Op Mode Ra Rb Byte r Little Endian 32-bit addr R0-R31 32 bit Byte r Little Endian 32-bit addr R0-R31 32 bit Before State After State Machine state:, memory, registers UTCS 352, Lecture 10 3 Simplify for Understanding Let s abstract & simplify: 9 MIPS instructions from the three categories: memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j add $8, $17, $18 Format: 000000 10001 10010 01000 00000 100000 op rs rt rd shamt funct What state & logic do we need to execute instructions? UTCS 352, Lecture 10 2
What do we need to execute instructions? Which instruction? instruction memory, : beq, j Which registers? register storage file Which Math? combinational logic: add,sub, and,or,slt Which data? memory: lw, sw UTCS 352, Lecture 10 5 Remember: State & Clocking Review Clocking methodology defines when to read/write a signal An edge-triggered methodology Typical execution read contents of state elements send values through combinational logic write results to one or more state elements No control: always write or Control the Write (write only on 1 ) always write control State element 1 Combinational logic State element 2 clock one clock cycle UTCS 352, Lecture 10 6 3
What is Execution? 5 logical steps IF: fetch instruction ID/R: decode instruction and read registers EX: execute (add, sub, ) MEM: access memory WB: store result (write back) I-Fetch Decode Execute Write Result UTCS 352, Lecture 10 7 Fetch the Next read the instruction from the update the to hold the address of the next instruction ress No write control because The processor updates the every cycle The processor reads instruction memory every cycle UTCS 352, Lecture 10 8
Decode the send the opcode of the fetched instruction and function field bits to the control unit Control Unit r 1 r 2 Data 1 read two values from the identifiers are in the instruction UTCS 352, Lecture 10 9 Executing Branch Operations compare registers + compute branch target Shift left 2 Branch target address ALU control r 1 r 2 Data 1 ALU zero (to branch control logic) Sign UTCS 352, Lecture 10 16 Extend 32 10 5
Executing Jump Operations replace the lower 28 bits of the with the lower 26 bits of the fetched instruction shifted left by 2 bits ress 26 Shift left 2 28 Jump address UTCS 352, Lecture 10 11 Executing R Format Operations R format operations (add, sub, slt, and, or) 31 25 20 15 10 5 0 R-type: op rs rt rd shamt funct perform the (op and funct) operation on values in rs and rt store the result back into the (into location rd) RegWrite ALU control r 1 r 2 Data 1 ALU overflow zero The is not written every cycle (e.g. sw), so we need an explicit write control signal for the UTCS 352, Lecture 10 12 6
Executing Load and Store Operations compute memory address: add base register (read from during decode) to 16-bit signed-extended offset field store write to Data value (read from during decode) load write to value, read from Data RegWrite ALU control MemWrite r 1 r 2 Data 1 overflow zero ALU ress Data Data Sign 16 Extend 32 Mem UTCS 352, Lecture 10 13 Summary Break down of instruction execution and logic based on needed functionality Next Time Putting it all together and adding control logic Pipelining Homework # is due Tuesday March 2, 2010 ing: P&H.5-6 UTCS 352, Lecture 10 1 7