LY62L K X 16 BIT LOW POWER CMOS SRAM

Y6225716 256K 16 BIT OW POWER CMOS SRAM REVISION ISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Apr.19.2006 Rev. 2.0 Revised ISB(max) : 0.5mA => 1.25mA May.11.2006 Rev. 2.1 Adding 44-pin TSOP-II Jul.5.2006 Rev. 2.2 Adding 48-ball BGA Dec.20.2006 Rev. 2.3 Revised IDR Deleted Spec. Added S Spec. Revised Test Condition of ICC/ISB1/IDR Mar.3.2008 Revised VTERM to VT1 and VT2 Rev. 2.4 Added I SB1 /I DR values when T A = 25 and T A = 40 Revised FEATURES & ORDERING INFORMATION ead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSODER in ABSOUTE MAIMUN RATINGS Rev. 2.5 Revised PACKAGE OUTINE DIMENSION in page 13 May.6.2010 Mar.30.2009 Rev. 2.6 Revised ORDERING INFORMATION in page 14 Aug.30.2010 Rev. 2.7 Corrected ORDERING INFORMATION Typo. May.20.2016 Deleted WRITE CYCE Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions in page 9 Jun.29.2016 yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 0

Y6225716 256K 16 BIT OW POWER CMOS SRAM FEATURES Fast access time : 45/55/70ns ow power consumption: Operating current : 40/30/20mA (TYP.) Standby current : 2 A (TYP.) -version 1 A (TYP.) S-version Single 2.7V ~ 3.6V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# (DQ0 ~ DQ7) UB# (DQ8 ~ DQ15) Data retention voltage : 1.5V (MIN.) Green package available Package : 44-pin 400 mil TSOP II 48-pin 12mm x 20mm TSOP I 48-ball 6mm x 8mm TFBGA GENERA DESCRIPTION The Y6225716 is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The Y6225716 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The Y6225716 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TT compatible PRODUCT FAMIY Product Operating Power Dissipation Vcc Range Speed Family Temperature Standby(ISB1,TYP.) Operating(Icc,TYP.) Y6225716 0 ~ 70 2.7 ~ 3.6V 45/55/70ns 2µA()/1µA(S) 40/30/20mA Y6225716(E) -20 ~ 80 2.7 ~ 3.6V 45/55/70ns 2µA()/1µA(S) 40/30/20mA Y6225716(I) -40 ~ 85 2.7 ~ 3.6V 45/55/70ns 2µA()/1µA(S) 40/30/20mA yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 1

Y6225716 256K 16 BIT OW POWER CMOS SRAM FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION SYMBO DESCRIPTION Vcc Vss A0 - A17 Address Inputs DQ0 DQ15 Data Inputs/Outputs A0-A17 DECODER 256Kx16 MEMORY ARRAY CE#, CE2 WE# Chip Enable Input Write Enable Input OE# Output Enable Input B# ower Byte Control UB# Upper Byte Control VCC Power Supply DQ0-DQ7 ower Byte DQ8-DQ15 Upper Byte I/O DATA CIRCUIT COUMN I/O VSS Ground CE# CE2 WE# OE# B# UB# CONTRO CIRCUIT yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 2

Y6225716 256K 16 BIT OW POWER CMOS SRAM PIN CONFIGURATION A4 A3 A2 A1 A0 CE# DQ0 DQ1 DQ2 DQ3 Vcc Vss DQ4 DQ5 DQ6 DQ7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Y6225716 22 23 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 A5 A6 A7 OE# UB# B# DQ15 DQ14 DQ13 DQ12 Vss Vcc DQ11 DQ10 DQ9 DQ8 CE2 A8 A9 A10 A11 A12 TSOP II A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# CE2 NC UB# B# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Y6225716 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC Vss DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0 TSOP I yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 3

Y6225716 256K 16 BIT OW POWER CMOS SRAM A B# OE# A0 A1 A2 CE2 B DQ8 UB# A3 A4 CE# DQ0 C D E F DQ9 DQ10 A5 Vss DQ11 A17 Vcc DQ12 NC DQ14 DQ13 A14 A6 A7 A16 A15 DQ1 DQ3 DQ4 DQ5 DQ2 Vcc Vss DQ6 Y6225716 G DQ15 NC A12 A13 WE# DQ7 NC A8 A9 A10 A11 NC 1 2 3 4 5 6 TFBGA(See through with Top View) TFBGA(Top View) ABSOUTE MAIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V 0 to 70(C grade) Operating Temperature TA -20 to 80(E grade) -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUT TABE Standby MODE CE# CE2 OE# WE# B# UB# Output Disable Read Write Note: = VI, = VI, = Don't care. I/O OPERATION DQ0-DQ7 DQ8-DQ15 igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z D OUT igh Z D OUT D IN igh Z D IN igh Z igh Z D OUT D OUT igh Z D IN D IN SUPPY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 4

Y6225716 256K 16 BIT OW POWER CMOS SRAM DC EECTRICA CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MA. UNIT Supply Voltage VCC 2.7 3.0 3.6 V Input igh Voltage VI *1 2.2 - VCC+0.3 V Input ow Voltage VI *2-0.2-0.6 V Input eakage Current II VCC VIN VSS - 1-1 µa Output eakage VCC VOUT VSS, IO Current Output Disabled - 1-1 µa Output igh Voltage VO IO = -1mA 2.2 2.7 - V Output ow Voltage VO IO = 2mA - - 0.4 V Cycle time = Min. - 45-40 50 ma ICC CE# = VI and CE2 = VI, II/O = 0mA - 55-30 40 ma Average Operating Power supply Current Standby Power Supply Current ICC1 ISB ISB1 Other pins at VI or VI Cycle time = 1µs CE# 0.2V and CE2 VCC-0.2V,, II/O = 0mA Other pins at 0.2V or VCC-0.2V CE# = VI or CE2 = VI, other pins at VI or VI CE# VCC-0.2V or CE2 0.2V Others at 0.2V or VCC - 0.2V Notes: 1. VI(max) = VCC + 3.0V for pulse width less than 10ns. 2. VI(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 5. This parameter is measured at VCC = 3.0V - 70-20 30 ma - 4 5 ma - 0.3 1.25 ma - 2 15 µa E/I - 2 20 µa S *5 SE *5 25-1 3 µa SI *5 40-1 3 µa S - 1 10 µa SE/SI - 1 12 µa yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 5

Y6225716 256K 16 BIT OW POWER CMOS SRAM CAPACITANCE (TA = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MA UNIT Input Capacitance CIN - 6 pf Input/Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse evels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IO/IO = -1mA/2mA AC EECTRICA CARACTERISTICS (1) READ CYCE PARAMETER SYM. Y6225716-45 Y6225716-55 Y6225716-70 UNIT MIN. MA. MIN. MA. MIN. MA. Read Cycle Time trc 45-55 - 70 - ns Address Access Time taa - 45-55 - 70 ns Chip Enable Access Time tace - 45-55 - 70 ns Output Enable Access Time toe - 25-30 - 35 ns Chip Enable to Output in ow-z tcz* 10-10 - 10 - ns Output Enable to Output in ow-z toz* 5-5 - 5 - ns Chip Disable to Output in igh-z tcz* - 15-20 - 25 ns Output Disable to Output in igh-z toz* - 15-20 - 25 ns Output old from Address Change to 10-10 - 10 - ns B#, UB# Access Time tba - 45-55 - 70 ns B#, UB# to igh-z Output tbz* - 20-25 - 30 ns B#, UB# to ow-z Output tbz* 10-10 - 10 - ns (2) WRITE CYCE PARAMETER SYM. Y6225716-45 Y6225716-55 Y6225716-70 UNIT MIN. MA. MIN. MA. MIN. MA. Write Cycle Time twc 45-55 - 70 - ns Address Valid to End of Write taw 40-50 - 60 - ns Chip Enable to End of Write tcw 40-50 - 60 - ns Address Set-up Time tas 0-0 - 0 - ns Write Pulse Width twp 35-45 - 55 - ns Write Recovery Time twr 0-0 - 0 - ns Data to Write Time Overlap tdw 20-25 - 30 - ns Data old from End of Write Time td 0-0 - 0 - ns Output Active from End of Write tow* 5-5 - 5 - ns Write to Output in igh-z twz* - 15-20 - 25 ns B#, UB# Valid to End of Write tbw 35-45 - 60 - ns *These parameters are guaranteed by device characterization, but not production tested. yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 6

Y6225716 256K 16 BIT OW POWER CMOS SRAM TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) Address trc taa to Dout Previous Data Valid Data Valid READ CYCE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Address trc CE# taa CE2 tace B#,UB# tba OE# tbz tcz toz toe to toz tbz tcz Dout igh-z Data Valid igh-z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, B# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 7

Y6225716 256K 16 BIT OW POWER CMOS SRAM WRITE CYCE 1 (WE# Controlled) (1,2,4,5) twc Address taw CE# tcw CE2 tbw B#,UB# tas twp twr WE# twz tow Dout (4) igh-z (4) tdw td Din Data Valid WRITE CYCE 2 (CE# and CE2 Controlled) (1,4,5) Address twc taw CE# tas twr CE2 tcw tbw B#,UB# twp WE# Dout twz (4) igh-z tdw td Din Data Valid yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 8

Y6225716 256K 16 BIT OW POWER CMOS SRAM WRITE CYCE 3 (B#,UB# Controlled) (1,4,5) twc Address taw twr CE# tas tcw CE2 tbw B#,UB# twp WE# Dout (4) twz igh-z tdw td Din Data Valid Notes : 1.A write occurs during the overlap of a low CE#, high CE2, low WE#, B# or UB# = low. 2.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 3.During this period, I/O pins are in the output state, and input signals must not be applied. 4.If the CE#, B#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 5.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 9

Y6225716 256K 16 BIT OW POWER CMOS SRAM DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MA. UNIT VCC for Data Retention VDR CE# VCC - 0.2V or CE2 0.2V 1.5-3.6 V - 1.0 12 µa E/I - 1.0 16 µa Data Retention Current IDR VCC = 1.5V CE# VCC - 0.2V or CE2 0.2V Other pins at 0.2V or VCC-0.2V S SE SI 25-0.5 2.5 µa 40-0.5 2.5 µa S - 0.5 8 µa SE/SI - 0.5 10 µa Chip Disable to Data See Data Retention tcdr 0 - - ns Retention Time Waveforms (below) Recovery Time tr trc* - - ns trc* = Read Cycle Time DATA RETENTION WAVEFORM ow Vcc Data Retention Waveform (1) (CE# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr CE# VI CE# Vcc-0.2V VI ow Vcc Data Retention Waveform (2) (CE2 controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr CE2 VI CE2 0.2V VI ow Vcc Data Retention Waveform (3) (B#, UB# controlled) VDR 1.5V Vcc Vcc(min.) Vcc(min.) tcdr tr B#,UB# VI B#,UB# Vcc-0.2V VI yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 10

Y6225716 256K 16 BIT OW POWER CMOS SRAM PACKAGE OUTINE DIMENSION 44-pin 400mil TSOP Ⅱ Package Outline Dimension SYMBOS DIMENSIONS IN MIMETERS DIMENSIONS IN MIS MIN. NOM. MA. MIN. NOM. MA. A - - 1.20 - - 47.2 A1 0.05 0.10 0.15 2.0 3.9 5.9 A2 0.95 1.00 1.05 37.4 39.4 41.3 b 0.30-0.45 11.8-17.7 c 0.12-0.21 4.7-8.3 D 18.212 18.415 18.618 717 725 733 E 11.506 11.760 12.014 453 463 473 E1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5-0.40 0.50 0.60 15.7 19.7 23.6 ZD - 0.805 - - 31.7 - y - - 0.076 - - 3 Θ 0 o 3 o 6 o 0 o 3 o 6 o yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 11

Y6225716 256K 16 BIT OW POWER CMOS SRAM 48-pin 12mm x 20mm TSOP I Package Outline Dimension yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 12

Y6225716 256K 16 BIT OW POWER CMOS SRAM 48-ball 6mm 8mm TFBGA Package Outline Dimension yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 13

Y6225716 256K 16 BIT OW POWER CMOS SRAM ORDERING INFORMATION Package Type 44Pin(400mil) TSOP II Access Time (Speed)(ns) Power Type 45 Special Ultra ow Power 55 Special Ultra ow Power 70 Special Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray Y6225716M-45S Y6225716M-45ST -20 ~80 Tray Y6225716M-45SE Y6225716M-45SET -40 ~85 Tray Y6225716M-45SI Y6225716M-45SIT Ultra ow Power 0 ~70 Tray Y6225716M-45 Y6225716M-45T -20 ~80 Tray Y6225716M-45E Y6225716M-45ET -40 ~85 Tray Y6225716M-45I Y6225716M-45IT 0 ~70 Tray Y6225716M-55S Y6225716M-55ST -20 ~80 Tray Y6225716M-55SE Y6225716M-55SET -40 ~85 Tray Y6225716M-55SI Y6225716M-55SIT Ultra ow Power 0 ~70 Tray Y6225716M-55 Y6225716M-55T -20 ~80 Tray Y6225716M-55E Y6225716M-55ET -40 ~85 Tray Y6225716M-55I Y6225716M-55IT 0 ~70 Tray Y6225716M-70S Y6225716M-70ST -20 ~80 Tray Y6225716M-70SE Y6225716M-70SET -40 ~85 Tray Y6225716M-70SI Y6225716M-70SIT Ultra ow Power 0 ~70 Tray Y6225716M-70 Y6225716M-70T -20 ~80 Tray Y6225716M-70E Y6225716M-70ET -40 ~85 Tray Y6225716M-70I Y6225716M-70IT yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 14

Y6225716 256K 16 BIT OW POWER CMOS SRAM ORDERING INFORMATION Package Type 48-Pin 12mmx20mm TSOP I Access Time (Speed)(ns) Power Type 45 Special Ultra ow Power 55 Special Ultra ow Power 70 Special Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray Y6225716-45S Y6225716-45ST -20 ~80 Tray Y6225716-45SE Y6225716-45SET -40 ~85 Tray Y6225716-45SI Y6225716-45SIT Ultra ow Power 0 ~70 Tray Y6225716-45 Y6225716-45T -20 ~80 Tray Y6225716-45E Y6225716-45ET -40 ~85 Tray Y6225716-45I Y6225716-45IT 0 ~70 Tray Y6225716-55S Y6225716-55ST -20 ~80 Tray Y6225716-55SE Y6225716-55SET -40 ~85 Tray Y6225716-55SI Y6225716-55SIT Ultra ow Power 0 ~70 Tray Y6225716-55 Y6225716-55T -20 ~80 Tray Y6225716-55E Y6225716-55ET -40 ~85 Tray Y6225716-55I Y6225716-55IT 0 ~70 Tray Y6225716-70S Y6225716-70ST -20 ~80 Tray Y6225716-70SE Y6225716-70SET -40 ~85 Tray Y6225716-70SI Y6225716-70SIT Ultra ow Power 0 ~70 Tray Y6225716-70 Y6225716-70T -20 ~80 Tray Y6225716-70E Y6225716-70ET -40 ~85 Tray Y6225716-70I Y6225716-70IT yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 15

Y6225716 256K 16 BIT OW POWER CMOS SRAM ORDERING INFORMATION Package Type 48-ball (6mmx8mm) TFBGA Access Time (Speed)(ns) Power Type 45 Special Ultra ow Power 55 Special Ultra ow Power 70 Special Ultra ow Power Temperature Range( ) Packing Type yontek Item No. 0 ~70 Tray Y6225716G-45S Y6225716G-45ST -20 ~80 Tray Y6225716G-45SE Y6225716G-45SET -40 ~85 Tray Y6225716G-45SI Y6225716G-45SIT Ultra ow Power 0 ~70 Tray Y6225716G-45 Y6225716G-45T -20 ~80 Tray Y6225716G-45E Y6225716G-45ET -40 ~85 Tray Y6225716G-45I Y6225716G-45IT 0 ~70 Tray Y6225716G-55S Y6225716G-55ST -20 ~80 Tray Y6225716G-55SE Y6225716G-55SET -40 ~85 Tray Y6225716G-55SI Y6225716G-55SIT Ultra ow Power 0 ~70 Tray Y6225716G-55 Y6225716G-55T -20 ~80 Tray Y6225716G-55E Y6225716G-55ET -40 ~85 Tray Y6225716G-55I Y6225716G-55IT 0 ~70 Tray Y6225716G-70S Y6225716G-70ST -20 ~80 Tray Y6225716G-70SE Y6225716G-70SET -40 ~85 Tray Y6225716G-70SI Y6225716G-70SIT Ultra ow Power 0 ~70 Tray Y6225716G-70 Y6225716G-70T -20 ~80 Tray Y6225716G-70E Y6225716G-70ET -40 ~85 Tray Y6225716G-70I Y6225716G-70IT yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 16

Y6225716 256K 16 BIT OW POWER CMOS SRAM TIS PAGE IS EFT BANK INTENTIONAY. yontek Inc. reserves the rights to change the specifications and products without notice. 2F, No17, Industry E. Rd. II, Science-Based Industrial Park, sinchu 300, Taiwan. TE: 886-3-6668838 FA: 886-3-6668836 17