Behavioral Modelig i Verilog COE 202 Digital Logic Desig Dr. Muhamed Mudawar Kig Fahd Uiversity of Petroleum ad Mierals
Presetatio Outlie Itroductio to Dataflow ad Behavioral Modelig Verilog Operators Module Parameters Modelig Adders, Comparators, Multiplexers Always Block with Sesitivity List Procedural Statemets: IF ad CASE Modelig Decoder, Priority Ecoder, ad ALU Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 2
Verilog Four-Valued Logic Verilog Value Set cosists of four basic values: 0 represets a logic zero, or false coditio 1 represets a logic oe, or true coditio X represets a ukow logic value Z represets a high-impedace value x or X represets a ukow or uiitialized value z or Z represets the output of a disabled tri-state buffer Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 3
Nets ad Variables Verilog has two major data types: 1. Net data types: are coectios betwee parts of a desig 2. Variable data types: ca store data values The wire is a et data type (physical coectio) A wire caot store the value of a procedural assigmet However, a wire ca be drive by cotiuous assigmet The reg is a variable data type Ca store the value of a procedural assigmet However, caot be drive by cotiuous assigmet Other variable types: iteger, time, real, ad realtime Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 4
Modelig Circuits i Verilog Four levels of modelig circuits i Verilog 1. Gate-Level Modelig Lowest-level modelig usig Verilog primitive gates 2. Structural Modelig usig module istatiatio Describes the structure of a circuit with modules at differet levels 3. Dataflow Modelig usig cocurret assig statemets Describes the flow of data betwee iput ad output 4. Behavioral Modelig usig procedural blocks ad statemets Describes what the circuit does at a higher level of abstractio Ca also mix differet models i the same desig Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 5
Dataflow ad Behavioral Modelig Dataflow Modelig usig Cotiuous Assigmet Used mostly for describig Boolea equatios ad combiatioal logic Verilog provides a rich set of operators Ca describe: adders, comparators, multiplexers, etc. Sythesis tool ca map a dataflow model ito a target techology Behavioral Modelig usig Procedural Blocks ad Statemets Describes what the circuit does at a fuctioal ad algorithmic level Ecourages desigers to rapidly create a prototype Ca be verified easily with a simulator Some procedural statemets are sythesizable (Others are NOT) Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 6
Cotiuous Assigmet The assig statemet defies cotiuous assigmet Sytax: assig [#delay] et_ame = expressio; Assigs expressio value to et_ame (wire or output port) The optioal #delay specifies the delay of the assigmet Cotiuous assigmet statemets are cocurret Ca appear i ay order iside a module Cotiuous assigmet ca model combiatioal circuits Describes the flow of data betwee iput ad output Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 7
Verilog Operators Bitwise Operators ~a Bitwise NOT a & b Bitwise AND a b Bitwise OR a ^ b Bitwise XOR a ~^ b Bitwise XNOR a ^~ b Same as ~^ Arithmetic Operators a + b ADD a b Subtract -a Negate a * b Multiply a / b Divide a % b Remaider Relatioal Operators a == b Equality a!= b Iequality a < b Less tha a > b Greater tha a <= b Less or equal a >= b Greater or equal Reductio Operators &a AND all bits a OR all bits ^a XOR all bits ~&a NAND all bits ~ a NOR all bits ~^a XNOR all bits Shift Operators Miscellaeous Operators a << Shift Left sel?a:b Coditioal a >> Shift Right {a, b} Cocateate Reductio operators produce a 1-bit result Relatioal operators produce a 1-bit result {a, b} cocateates the bits of a ad b Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 8
Bit Vectors i Verilog A Bit Vector is multi-bit declaratio that uses a sigle ame A Bit Vector is specified as a Rage [msb:lsb] msb is most-sigificat bit ad lsb is least-sigificat bit Examples: iput [15:0] A; output [0:15] B; // A is a 16-bit iput vector // Bit 0 is most-sigificat bit wire [3:0] W; // Bit 3 is most-sigificat bit Bit select: W[1] is bit 1 of W Part select: A[11:8] is a 4-bit select of A with rage [11:8] The part select rage must be cosistet with vector declaratio Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 9
Reductio Operators module Reduce ( iput [3:0] A, B, output X, Y, Z ); // A, B are iput vectors, X, Y, Z are 1-bit outputs // X = A[3] A[2] A[1] A[0]; assig X = A; // Y = B[3] & B[2] & B[1] & B[0]; assig Y = &B; // Z = X & (B[3] ^ B[2] ^ B[1] ^ B[0]); assig Z = X & (^B); edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 10
Cocateatio Operator { } module Cocateate ( iput [7:0] A, B, output [7:0] X, Y, Z ); // A, B are iput vectors, X, Y, Z are output vectors // X = A is right-shifted 3 bits usig { } operator assig X = {3'b000, A[7:3]}; // Y = A is right-rotated 3 bits usig { } operator assig Y = {A[2:0], A[7:3]}; // Z = selectig ad cocateatig bits of A ad B assig Z = {A[5:4], B[6:3], A[1:0]}; edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 11
Iteger Literals (Costat Values) Sytax: [size]['base]value size (optioal) is the umber of bits i the value 'base ca be: 'b(biary), 'o(octal), 'd(decimal), or 'h(hex) value ca be i biary, octal, decimal, or hexadecimal If the 'base is ot specified the decimal value Examples: 8'b1011_1101 (8-bit biary), 'ha3f0 (16-bit hexadecimal) 16'o56377 (16-bit octal), 32'd999 (32-bit decimal) The uderscore _ ca be used to ehace readability of value Whe size is fewer bits tha value, upper bits are trucated Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 12
Ripple Carry Adder Usig idetical copies of a full adder to build a large adder The cell (iterative block) is a full adder Adds 3 bits: a i, b i, c i, Computes: Sum s i ad Carry-out c i+1 Carry-out of cell i becomes carry-i to cell (i +1) a -1 b -1 a 1 b 1 a 0 b 0 a i b i c Full Adder c -1... c 2 Full Adder c 1 Full Adder c 0 c i+1 Full Adder c i s -1 s 1 s 0 s i Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 13
16-Bit Adder with Array Istatiatio // Iput ports: 16-bit a ad b, 1-bit ci (carry iput) // Output ports: 16-bit sum, 1-bit cout (carry output) module Adder_16 (iput [15:0] a, b, iput ci, output [15:0] sum, output cout); wire [16:0] c; assig c[0] = ci; assig cout = c[16]; // carry bits // carry iput // carry output // Istatiate a array of 16 Full Adders // Each istace [i] is coected to bit select [i] Full_Adder FA [15:0] (a[15:0], b[15:0], c[15:0], c[16:1], sum[15:0]); edmodule Array Istatiatio of idetical modules by a sigle statemet Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 14
16-Bit Adder with Cotiuous Assigmet // Iput ports: 16-bit a ad b, 1-bit ci (carry iput) // Output ports: 16-bit sum, 1-bit cout (carry output) module Adder_16 (iput [15:0] a, b, iput ci, output [15:0] sum, output cout); wire [16:0] c; assig c[0] = ci; assig cout = c[16]; // carry bits // carry iput // carry output // assigmet of 16-bit vectors assig sum[15:0] = (a[15:0] ^ b[15:0]) ^ c[15:0]; assig c[16:1] = (a[15:0] & b[15:0]) (a[15:0] ^ b[15:0]) & c[15:0]; edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 15
16-bit Adder with the + Operator module Adder16 ( iput [15:0] A, B, iput ci, output [15:0] Sum, output cout ); // A ad B are 16-bit iput vectors // Sum is a 16-bit output vector // {cout, Sum} is a cocateated 17-bit vector // A + B + ci is 16-bit additio + iput carry // The + operator is traslated ito a adder assig {cout, Sum} = A + B + ci; edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 16
Modelig a Parametric -bit Adder // Parametric -bit adder, default value for = 16 module Adder #(parameter = 16) ( iput [-1:0] A, B, iput ci, output [-1:0] Sum, output cout ); // A ad B are -bit iput vectors // Sum is a -bit output vector // The + operator is traslated ito a -bit adder // Oly oe assig statemet is used assig {cout, Sum} = A + B + ci; edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 17
Istatiatig Adders of Various Sizes // Istatiate a 16-bit adder (parameter = 16) // A1, B1, ad Sum1 must be 16-bit vectors Adder #(16) adder16 (A1, B1, Ci1, Sum1, Cout1); // Istatiate a 32-bit adder (parameter = 32) // A2, B2, ad Sum2 must be 32-bit vectors Adder #(32) adder32 (A2, B2, Ci2, Sum2, Cout2); // If parameter is ot specified, it defaults to 16 Adder adder16 (A1, B1, Ci1, Sum1, Cout1); Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 18
Modelig a Magitude Comparator // -bit magitude comparator, No default value for module Comparator #(parameter ) (iput [-1:0] A, B, output GT, EQ, LT); // A ad B are -bit iput vectors (usiged) // GT, EQ, ad LT are 1-bit outputs assig GT = (A > B); assig EQ = (A == B); assig LT = (A < B); edmodule A[ 1:0] B[ 1:0] -bit Magitude Comparator GT EQ LT Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 19
Istatiatig Comparators of Various Sizes // Istatiate a 16-bit comparator ( = 16) // A1 ad B1 must be declared as 16-bit vectors Comparator #(16) comp16 (A1, B1, GT1, EQ1, LT1); // Istatiate a 32-bit comparator ( = 32) // A2 ad B2 must be declared as 32-bit vectors Comparator #(32) comp32 (A2, B2, GT2, EQ2, LT2); // WRONG Istatiatio: Must specify parameter Comparator comp32 (A2, B2, GT2, EQ2, LT2); Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 20
Coditioal Operator Sytax: Boolea_expr? True_expressio : False_expressio If Boolea_expr is true the select True_expressio Else select False_Expressio Examples: assig max = (a>b)? a : b; // maximum of a ad b assig mi = (a>b)? b : a; // miimum of a ad b Coditioal operators ca be ested Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 21
Modelig a 2x1 Multiplexer // Parametric 2x1 Mux, default value for = 1 module Mux2 #(parameter = 1) ( iput [-1:0] A, B, iput sel, A output [-1:0] Z); B // A ad B are -bit iput vectors // Z is the -bit output vector // if (sel==0) Z = A; else Z = B; 0 1 // Coditioal operator used for selectio assig Z = (sel == 0)? A : B; edmodule sel Z Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 22
Modelig a 4x1 Multiplexer // Parametric 4x1 Mux, default value for = 1 module Mux4 #(parameter = 1) ( iput [-1:0] A, B, C, D, iput [1:0] sel, A output [-1:0] Z ); B // sel is a 2-bit vector C // Nested coditioal operators D assig Z = (sel[1] == 0)? ((sel[0] == 0)? A : B) : ((sel[0] == 0)? C : D); edmodule 0 1 2 3 2 sel Z Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 23
Behavioral Modelig Uses procedural blocks ad procedural statemets There are two types of procedural blocks i Verilog 1. The iitial block Executes the eclosed statemet(s) oe time oly 2. The always block Executes the eclosed statemet(s) repeatedly util simulatio termiates The body of the iitial ad always blocks is procedural Ca eclose oe or more procedural statemets Procedural statemets are surrouded by begi ed Multiple procedural blocks ca appear i ay order iside a module ad ru i parallel iside the simulator Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 24
Example of Iitial ad Always Blocks module behave; reg clk; // 1-bit variable reg [15:0] A; // 16-bit variable iitial begi // executed oce clk = 0; // iitialize clk A = 16'h1234; // iitialize A #200 $fiish ed always begi // executed always #10 clk = ~clk; // ivert clk every 10 s ed always begi // executed always #20 A = A + 1; // icremet A every 20 s ed edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 25
Always Block with Sesitivity List Sytax: always @(sesitivity list) begi procedural statemets ed A always block ca have a sesitivity list Sesitivity list is a list of sigals: @(sigal1, sigal2, ) The sesitivity list triggers the executio of the always block Whe there is a chage of value i ay listed sigal Otherwise, the always block does othig util aother chage occurs o a sigal i the sesitivity list Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 26
Sesitivity List for Combiatioal Logic For combiatioal logic, the sesitivity list must iclude: ALL the sigals that are read iside the always block Example: A, B, ad sel must be i the sesitivity list below: always @(A, B, sel) begi if (sel == 0) Z = A; else Z = B; ed A, B, ad sel are read iside the always block Combiatioal logic ca also use: @(*) or @* @(*) is automatically sesitive to all the sigals that are read iside the always block Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 27
If Statemet The if statemet is procedural Ca oly be used iside a procedural block Sytax: if (expressio) statemet [ else statemet ] The else part is optioal A statemet ca be simple or compoud A compoud statemet is surrouded by begi... ed if statemets ca be ested Ca be ested uder if or uder else part Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 28
Modelig a 2x1 Multiplexer // Behavioral Modelig of a Parametric 2x1 Mux module Mux2 #(parameter = 1) ( iput [-1:0] A, B, iput sel, output reg [-1:0] Z); // Output Z must be of type reg // Sesitivity list = @(A, B, sel) always @(A, B, sel) begi if (sel == 0) Z = A; else Z = B; ed A B 0 1 Z edmodule sel Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 29
Modelig a 3x8 Decoder module Decoder3x8 (iput [2:0] A, output reg [7:0] D); // Sesitivity list = @(A) always @(A) begi if (A == 0) D = 8'b00000001; else if (A == 1) D = 8'b00000010; else if (A == 2) D = 8'b00000100; else if (A == 3) D = 8'b00001000; else if (A == 4) D = 8'b00010000; else if (A == 5) D = 8'b00100000; else if (A == 6) D = 8'b01000000; else D = 8'b10000000; ed edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 30
Modelig a 4x2 Priority Ecoder module Priority_Ecoder4x2 (iput [3:0] D, output reg V, output reg [1:0] A); // sesitivity list = @(D) always @(D) begi if (D[3]) {V, A} = 3'b111; else if (D[2]) {V, A} = 3'b110; else if (D[1]) {V, A} = 3'b101; else if (D[0]) {V, A} = 3'b100; else {V, A} = 3'b000; ed edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 31
Modelig a Magitude Comparator // Behavioral Modelig of a Magitude Comparator module Comparator #(parameter = 1) (iput [-1:0] A, B, output reg GT, EQ, LT); // Sesitivity list = @(A, B) always @(A, B) begi if (A > B) {GT,EQ,LT}='b100; else if (A == B) A[ 1:0] -bit {GT,EQ,LT}='b010; Magitude else {GT,EQ,LT}='b001; ed edmodule B[ 1:0] Comparator GT EQ LT Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 32
Case Statemet The case statemet is procedural (used iside always block) Sytax: case (expressio) case_item1: statemet case_item2: statemet... default: statemet edcase The default case is optioal A statemet ca be simple or compoud A compoud statemet is surrouded by begi... ed Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 33
Modelig a Mux with a Case Statemet module Mux4 #(parameter = 1) ( iput [-1:0] A, B, C, D, iput [1:0] sel, output reg [-1:0] Z ); // @(*) is @(A, B, C, D, sel) always @(*) begi case (sel) 2'b00: Z = A; 2'b01: Z = B; 2'b10: Z = C; default: Z = D; edcase ed edmodule A B C D 0 1 2 3 2 sel Z Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 34
Modelig a Multifuctio ALU // Behavioral Modelig of a ALU module ALU #(parameter = 16) ( iput [-1:0] A, B, iput [1:0] F, output reg [-1:0] Z, output reg Cout ); // @(*) is @(A, B, F) always @(*) begi case (F) 2'b00: {Cout,Z} = A+B; 2'b01: {Cout,Z} = A-B; 2'b10: {Cout,Z} = A&B; default: {Cout,Z} = A B; edcase ed edmodule F [1:0] A [-1:0] ALU Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 35 2 ALU Symbol Cout Z [-1:0] B [-1:0]
Modelig a BCD to 7-Segmet Decoder module BCD_to_7Seg_Decoder ( iput [3:0] BCD, output reg [6:0] Seg ) always @(BCD) begi case (BCD) 0: Seg = 7'b1111110; 1: Seg = 7'b0110000; 2: Seg = 7'b1101101; 3: Seg = 7'b1111001; 4: Seg = 7'b0110011; 5: Seg = 7'b1011011; 6: Seg = 7'b1011111; 7: Seg = 7'b1110000; 8: Seg = 7'b1111111; 9: Seg = 7'b1111011; default: Seg = 7'b0000000; edcase ed edmodule Behavioral Modelig i Verilog COE 202 Digital Logic Desig Muhamed Mudawar slide 36