Instruction set of 05 /23/2016 ptkarule@rediffmail.com 1 Instruction set of 05 Instruction set is divided into various groups depending on the operations performed: 1. Data transfer 2. rithmetic 3. Logical 4. Bit manipulation 5. Branching (JMP) 6. Stack related (PUSH / POP) 7. Subroutine CLL & RET. Interrupt control /23/2016 ptkarule@rediffmail.com 2 1
Types of data transfer a) Data immediate to Register b) Register to Register c) Register to Memory location d) Data immediate to Memory location e) Memory location to Register f) Exchange of data between two registers g) Data transfer between up and I/O device /23/2016 ptkarule@rediffmail.com 3 Data transfer operation Data is copied from source to destination. Source data is not lost Destination old data is lost Source # bit # bit # 16 bit Register Register M.L. / 16 Destination Register M.L. Register pair Register M.L. Register /23/2016 ptkarule@rediffmail.com 4 2
format Source / 16 Destination Instruction format for INTEL is as follows: Mnemonics Operand1, Operand2 Mnemonics specify the operation Operand1 is the destination for result Operand2 is the source for data Instruction format for data transfer instruction Mnemonics Destination, Source /23/2016 ptkarule@rediffmail.com 5 a) Data immediate to Register 1. MVI Rd, bit data bit data Rd bit data any no. between 00H to FFH Destination register (,B,C,D,E,H & L) /23/2016 ptkarule@rediffmail.com 6 3
e.g. MVI C, 45H ; Move immediate data 45H into register C. 45 45 C e.g. MVI B, 5FH ; 5F B e.g. MVI L, 7H ; 7 L /23/2016 ptkarule@rediffmail.com 7 2. LXI Rp, 16 bit data 16 bit no. Rp 16 16 bit any no. between 0000H to FFFFH 16 bit register B-C, D-E, H-L, SP /23/2016 ptkarule@rediffmail.com 4
e.g. LXI B, 2350H 2350H B 23 C 50 e.g. LXI H, 67F9H 67F9H H 67 L F9 /23/2016 ptkarule@rediffmail.com 9 b) Register to Register 1. MOV Rd, Rs Rs Rs Source Register (,B,C,D,E,H & L) Rd Rd Destination Register (,B,C,D,E,H & L) /23/2016 ptkarule@rediffmail.com 10 5
e.g. MOV B, L B D H C E L L 34 5F 34 B /23/2016 ptkarule@rediffmail.com 11 Instruction Code /23/2016 ptkarule@rediffmail.com 12 6
Instruction Code Formation Seven bit Registers To select one register out of 7, 3 bit address is used Registers 3 bit address B 000 C 001 D 010 E 011 H 100 L 101 M 110 111 /23/2016 ptkarule@rediffmail.com 13 Instruction Code Format Every instruction is represented by its equivalent opcode bit operation code = Opcode = instruction code Opcode Format for MOV Rd, Rs D7 D6 D5 D4 D3 D2 D1 D0 0 1 D D D S S S Rd 3 bit destination register address Rs 3 bit source register address /23/2016 ptkarule@rediffmail.com 14 7
Instruction Code Formation ssemble the opcode of MOV B, L D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 1 0 1 B reg L reg ssembly Language MOV B, L ssembler or Hand Coding Machine Language 45H /23/2016 ptkarule@rediffmail.com 15 Instruction Code Formation ssemble the opcode for following instruction. MOV, B MOV C, E MOV L, D MOV H, /23/2016 ptkarule@rediffmail.com 16
Instruction Code Format Opcode Format for MVI Rd, bit data D7 D6 D5 D4 D3 D2 D1 D0 0 0 D D D 1 1 0 3 bit destination register address /23/2016 ptkarule@rediffmail.com 17 Instruction Code Format ssemble opcode for MVI C, 5FH D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 0 C reg ssembly Language MVI C, 5FH ssembler or Hand Coding Machine Language 0EH 5FH /23/2016 ptkarule@rediffmail.com 1 9
Instruction Code Formation ssemble the opcode for following instruction. MVI D, 46H MVI L, 33H MVI H, 50H MVI E, 7FH MVI, 00H /23/2016 ptkarule@rediffmail.com 19 Instruction Code Format Opcode Format for LXI Rp, 16 bit data D7 D6 D5 D4 D3 D2 D1 D0 0 0 Rp Rp 0 0 0 1 2 bit destination register pair address Rp 2 bit addr B C 00 D E 01 H L 10 SP 11 /23/2016 ptkarule@rediffmail.com 20 10
Instruction Code Format ssemble opcode for LXI B, 2150H D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 B-C Rp ssembly Language LXI B, 2150H ssembler or Hand Coding Machine Language 01H 50H 21H /23/2016 ptkarule@rediffmail.com 21 Instruction Code Formation ssemble the opcode for following instruction. LXI H, 3350H LXI D, 56FFH LXI SP, FFF0H /23/2016 ptkarule@rediffmail.com 22 11
Instruction Code Classification THREE types of instruction Single byte (Instruction without data) Double byte (Instruction with bit data) Triple byte (Instruction with 16 bit data / addr) Single byte opcode Double byte opcode bit data Triple byte opcode LS byte MS byte /23/2016 ptkarule@rediffmail.com 23 Instruction set cont.. /23/2016 ptkarule@rediffmail.com 24 12
Programmer s Model bit 0000H B C bit bit 0001H 0002H D E H L 05 µp bit bit bit FFFDH FFFEH FFFFH /23/2016 ptkarule@rediffmail.com 25 c) Register to Memory location 0000H 0001H B C D E H L 64KB Memory WRITE operation FFFFH /23/2016 ptkarule@rediffmail.com 26 13
c) Register to Memory location 1. ST 16 bit address 1 M. L. Source Destination? Source of data is fixed lways only () Only one specified Memory Location (1 M.L.) Out of 64K M.L. /23/2016 ptkarule@rediffmail.com 27 e.g. ST 2350H XX ; Store register data to M.L. ; whose address is 2350H XX ZZ 2350H Data e.g. MVI, 45H ST 2350H 45 Data ZZ 45 2350H /23/2016 ptkarule@rediffmail.com 2 14
e.g. MVI, 45H ST 2350H Memory W - Z ddress 23 50 16 2350H ZZ 45 XX 45 Data 05 µp /23/2016 ptkarule@rediffmail.com 29 e.g. 1) ST 5670H 2) Store B reg data to M. L. 3260H 3) Store E reg data to M. L. 7FF0H /23/2016 ptkarule@rediffmail.com 30 15
c) Register to Memory location 2. STX Rp (B C or D E is memory pointer ) Memory Rp ddress YY YY 16 YYYYH XX ZZ XX Data 05 µp /23/2016 ptkarule@rediffmail.com 31 e.g. MVI, 45H ; Store data 45H in CC LXI B, 2350H ; Store address in B-C STX B ; Store data of reg into M. L. B - C ddress 23 50 16 2350H ZZ 45 XX 45 05 µp Data Memory /23/2016 ptkarule@rediffmail.com 32 16
c) Register to Memory location 3. MOV M, Rs ( H L pair is a memory pointer ) Memory H - L ddress YY YY YYYYH XX ZZ 16 Rs XX Data 05 µp M /23/2016 ptkarule@rediffmail.com 33 e.g. MVI B, 45H LXI H, 2350H MOV M, B H - L 23 50 B 45 05 16 ddress 2350H Data 45 /23/2016 ptkarule@rediffmail.com 34 17
d) Data immediate to Memory location MVI M, bit data e.g LXI H, 450FH MVI M, 69H H - L 45 0F Z 69 16 ddress 450FH Data 69 05 /23/2016 ptkarule@rediffmail.com 35 e) Memory location to Register 0000H 0001H B C D E H L 64KB Memory RED operation FFFFH /23/2016 ptkarule@rediffmail.com 36 1
e) Memory location to Register 1. LD 16 bit address e.g. LD 7F54H W - Z ddress 7F 54 16 7F54H ZZ 45 60 45 05 µp Data Memory /23/2016 ptkarule@rediffmail.com 37 e) Memory location to Register 2. LDX Rp ( Rp is memory pointer ) Rp = B C or D E pair e.g. LXI D, 7F54H LDX D D - E 7F 54 30 05 16 ddress 7F54H Data 30 /23/2016 ptkarule@rediffmail.com 3 19
e) Memory location to Register 3. MOV Rs, M ( H L pair is a memory pointer ) e.g. LXI H, 7F54H MOV C, M H - L 7F 54 C 30 05 ddress 16 Data 7F54H 30 /23/2016 ptkarule@rediffmail.com 39 f) Exchange of data between two register pairs XCHG ; exchange data of D-E and H-L H - L 7F 54 D - E 50 35 /23/2016 ptkarule@rediffmail.com 40 20
16 bit Data transfer 1. SHLD 16 bit addr ;Store 16 bit data of H-L to two consecutive M. L.s e.g. SHLD 2150H H - L 43 7F Memory 7F 43 2150H 2151H /23/2016 ptkarule@rediffmail.com 41 16 bit Data transfer 2. LHLD 16 bit addr ;Load 16 bit data from two consecutive M. L.s to H - L pair e.g. LHLD 2150H 43 H - L 7F Memory 7F 43 2150H 2151H /23/2016 ptkarule@rediffmail.com 42 21
Summary Immediate Data Transfer MVI Rd, bit data LXI Rp, 16 bit data MVI M, bit Register to Register MOV Rd, Rs Register to Memory ST 16 bit addr STX Rp MOV M, Rs SHLD 16 bit addr Memory to Register LD 16 bit addr LDX Rp MOV Rd, M LHLD 16 bit addr /23/2016 ptkarule@rediffmail.com 43 ddressing modes ddressing mode means the way in which address of source of data and address for destination of result is specified in the Instruction. The different addressing modes are:- 1. Immediate addressing mode 2. Register addressing mode 3. Direct addressing mode 4. Indirect addressing mode 5. Implicit addressing mode /23/2016 ptkarule@rediffmail.com 44 22
1. Immediate addressing mode or 16 bit data required for executing the instruction is given in the instruction itself e.g. MVI,7H LXI H,564FH DI 45H SUI 40H CPI 55H NI 0FH ORI 66H /23/2016 ptkarule@rediffmail.com 45 2. Register addressing mode If or 16 bit data required for executing the instruction is present in register then name of that register is used in place of an operand in the instruction. e.g. MOV,B DD C SUB D CMP L N E OR H /23/2016 ptkarule@rediffmail.com 46 23
3. Direct addressing mode If or 16 bit data required for executing the instruction is present in memory location then 16 bit address of that memory location is used in place of an operand in the instruction. e.g. ST 2450H LD 6000H SHLD 2150H /23/2016 ptkarule@rediffmail.com 47 4. Indirect addressing mode If or 16 bit data required for executing the instruction is present in memory location and 16 bit address of that memory location is present in register pair hence name of Rp is used as a memory pointer. e.g. LXI B, 2450H STX B -- LXI D, 6000H LDX D /23/2016 ptkarule@rediffmail.com 4 24
5. Implicit addressing mode If operands are fixed then no operand is given in the instruction. e.g. XGHG D CM RL /23/2016 ptkarule@rediffmail.com 49 rithmetic & Logical Instructions 1. ddition 2. BCD addition 3. Subtraction 4. Increment 5. Decrement 6. ND operation 7. OR operation. XOR operation 9. NOT operation /23/2016 ptkarule@rediffmail.com 50 25
LU () + (X) () () X () Flags () LU () /23/2016 ptkarule@rediffmail.com 51 Flag Register Out of F/F s of flag register, 5 are used as flags to store status of result The five status flags are CY,ZF, SF,C & PF The flags are affected by the arithmetic and logical operations There position in the flag register is as follows S Z X C X P X CY /23/2016 ptkarule@rediffmail.com 52 26
ddition Operation 1. DD Rs ; dd data of Rs with cc X Rs CF + Y? X+Y Rs Source Register (,B,C,D, E,H,L & M) CF = 1; If result is > bit CF = 0; If result is bit /23/2016 ptkarule@rediffmail.com 53 ddition Operation e.g. Perform 45H + 72H and store result in E reg. MVI, 45H ; MVI B, 72H ; DD B ; MOV E, ; 0 1 0 0 0 1 0 1 + 0 1 1 1 0 0 1 0 1 0 1 1 0 1 1 1 45 B 72 CF 0 B7 B7 CF = 0, P = 1, C = 0, Z = 0, S = 1 /23/2016 ptkarule@rediffmail.com 54 E 27
ddition Operation 2. DI bit data ; dd immediate data to cc X + bit data (Y)? X+Y ny no Between 00H to FFH CF CF = 1; If result is > bit CF = 0; If result is bit /23/2016 ptkarule@rediffmail.com 55 ddition Operation e.g. Perform 45H + 72H and store result in M.L.2300H MVI, 45H ; DI 72H ; ST 2300H ; 45 B7 CF 0 XX B7 2300H /23/2016 ptkarule@rediffmail.com 56 2
Problem #1 Ten bytes are present in memory from address 2540H, Write program to add ten bytes and store result after the block Program logic Initialize the registers Pointer H-L 2540H Counter C 0H Sum Reg 00H 2540H 2541H 2542H 2543H 2544H 2545H 2546H 2547H 254H 2549H X0 X1 X2 X3 X4 X5 X6 X7 X X9 Steps dd data to CC Increment pointer Decrement Counter Repeat /23/2016 ptkarule@rediffmail.com 57 X0 Problem #1 (cont..) Program LXI H, 2540H ; SET POINTER MVI C, 0H ; SET COUNTER MVI, 00H ; CLER SUM REG L1: DD M ; DD DT INX H ; INCREMENT POINTER DCR C ; DECREMENT COUNTER JNZ L1 ; Jump if C!=00H (ZF=0) MOV M, ; STORE RESULT HLT /23/2016 ptkarule@rediffmail.com 5 29
Problem #2 10 bytes are present in MEMORY from address 2000H. Write program to transfer this data block from address 3200H onwards Program logic is H - L 2000H Source Pointer C 0H Counter D - E 3200H Destination Pointer 2000H 2001H 2002H 2003H 2004H 2005H 2006H 2007H 200H 2009H X0 X1 X2 X3 X4 X5 X6 X7 X X9 X0 X0 3200H 3201H 3202H 3203H 3204H 3205H 3206H 3207H 320H 3209H MEMORY MEMORY /23/2016 ptkarule@rediffmail.com 59 Program Problem #2 (cont..) LXI H, 2000H ; SET SOURCE POINTER LXI D, 3200H ; SET DEST. POINTER MVI C, 0H ; SET COUNTER L1: MOV, M ; GET DT STX D ; STORE DT INX H ; INCREMENT S_PTR INX D ; INCREMENT D_PTR DCR C ; DECREMENT COUNTER JNZ L1 HLT /23/2016 ptkarule@rediffmail.com 60 30