Index A Active buffer window (ABW), 34 35, 37, 39, 40 Adaptive data compression, 151 172 Adaptive routing, 26, 100, 114, 116 119, 121 123, 126 128, 135 137, 139, 144, 146, 158 Adaptive voltage scaling, 53 54 schemes, 46, 54 systems, 62, 64 Advanced extensible interface (AXI) bus, 179 Allocation, 7, 9, 23, 155, 169, 185, 186, 188, 191 193, 258, 277 Amplitude-shift-keying (ASK), 264 269, 271 Application latency, 176, 177 Application specific channel dependency graph (ASCDG), 124, 127 131, 133 Application specific domain, 135 Application specific routing, 122 Application specific routing algorithms (APSRA), 113 148 Arbiters, 22, 23, 28, 89, 100 102, 106, 158, 163, 188, 189, 235, 237 Arbitration, 7 13, 15, 17, 18, 76, 100, 101, 144, 145, 189, 235 238, 240, 243, 244, 248, 250, 278 unit, 100, 101 waveguide, 236, 237 ASCDG. See Application specific channel dependency graph ASK. See Amplitude-shift-keying Asymptotic zero-transition coding, 48 49 Asynchronous arbitration, 76 Asynchronous circuits, 73 Asynchronous communication, 71 106 Asynchronous controller, 103 Asynchronous design, 73 75, 78, 89, 100, 103, 106 Asynchronous design flow, 102 Asynchronous interface, 76 Asynchronous link, 75, 97, 103 Asynchronous logic, 76 Asynchronous pipeline, 92 Asynchronous router, 97, 102 Asynchronous signalling, 79 81 Asynchronous techniques, 75 B Bandwidth requirement, 114, 153, 177, 179, 183, 214, 216 Baseband, 258 260, 265 268 Benchmarks, 31, 32, 37, 38, 152, 163, 165, 168, 169, 201, 211, 215, 216, 218 220, 247 249 Best effort network, 97 Bimodal-length distribution, 155 Binary-phase-shift-keying (BPSK), 259, 265 Biput channel, 81 Bisection bandwidth, 16, 224, 248, 257 Bit-flips, 121 Bottleneck, 97, 224, 256 BPSK. See Binary-phase-shift-keying Broadcast, 4, 76, 153, 229, 236, 237, 239, 242, 243, 278 Buffering, 7, 182, 246 Bundled-data encoding, 87 Bus, 4 6, 9, 19, 46 49, 54, 60, 72, 76, 152 154, 175, 176, 178, 179, 190, 197, 201, 226, 237, 240, 248, 261, 273 275 Bus compression, 152, 153 Bus-Expander, 153 Bus-invert coding, 47, 48 281
282 Index C Cache capacity, 152, 153 Cache coherence, 35, 37, 162, 278 Cache compression, 152, 153 CACs. See Crosstalk avoidance codes Cacti, 162, 242 CAM. See Content-addressable memory CAM cells, 170 CDG. See Channel dependency graph C-elements, 82, 84 Channel bandwidth, 157, 225, 238, 265 Channel dependency, 127, 129 Channel dependency graph (CDG), 123, 124, 126 128, 147 Chip multi-processor (CMP), 34 37, 39, 151, 152, 154, 155, 158, 162 164, 166 170, 172, 223 252, 255 257, 261, 265, 272, 277 Circuit-switched data transfer, 7, 10, 13 Circuit-switched network, 4, 7, 9, 10, 15, 19, 96 Circuit-switching, 116, 200, 265 Clock distribution, 52, 97, 243 domains, 95 98 gating, 21, 24, 25 skew, 52, 73, 203, 210, 217 Clocked domains, 96, 98, 106 Clockless design, 74 Cluster regions, 132 CMOS nanophotonic, 223 252 CMP. See Chip multi-processor CMP simulator, 39, 162 Coarse grained power gating, 26 Coarse wavelength division multiplexing (CWDM), 227, 228 Coherence message, 155, 243 Common-mode noise reduction, 50 Communication based partitioning, 212 Communication graph, 123 128, 133 135 137, 147, 206, 211, 212 Completion detection, 78, 82 84, 86, 87, 90, 91 Compressed packet, 156, 169, 170 Compression technique, 125, 132, 133, 145, 146, 164, 166 Concurrent flows, 121 Congested channels, 116 Content-addressable memory (CAM), 154, 158, 170, 171 Contention-free latency, 157 Contention-look-ahead routing, 119 Control overhead, 121 Corona architecture, 240 247 Credit-based flow control, 155 Critical path, 9, 73, 92, 169, 207, 214 Crossbar, 10, 23, 52, 100, 144, 145, 155, 163, 207, 240 244, 248 251 switch, 22, 189 Crosstalk avoidance codes (CACs), 48 Crosstalk capacitance, 73 Current mode signaling, 46, 52 CWDM. See Coarse wavelength division multiplexing D Data compression, 151 172 consistency, 152 encoding technique, 75 flow control scheme, 75 propagation, 96 tokens, 92 validity, 77, 82 Datalink layer techniques, 47 49 Deadlock free routing, 114, 115, 118, 120, 122, 126, 147 Deadlocks, 10, 37, 100, 114 118, 121 127, 131, 147, 182 Decoding latency, 162 Decoding table, 152, 156, 158, 159, 161, 166, 168, 170, 171 Delay-insensitive circuits, 73 Delay insensitive codes, 82 Delay variability, 73 Dense wavelength division multiplexing (DWDM), 227, 228, 230, 236, 240, 242 244 Deterministic routing, 100, 116 118, 136, 138, 139, 144, 146, 158, 171 Dictionary, 164 Die stacking, 226, 231 Die-to-die, 73, 246 Differential signaling, 50 3D integration, 201, 202, 216 3D interconnects, 201 Direct-mapped cache, 158 Distributed routing, 7, 116 3D manufacturing process, 204 2D mesh, 7, 8, 10, 120, 121, 131, 137 143, 179, 182, 183, 226, 248 3D packaging, 239 3D stacking, 201, 245, 270 Dual-rail channel, 83 Dual-rail codes, 82, 92 Dual-rail logic, 82
Index 283 Dual-supply voltage design (dual-v DD ), 51 Dual-threashold voltage design (dual-v T ), 51 Dual-voltage buffers, 51 DVFS. See Dynamic voltage and frequency scaling DWDM. See Dense wavelength division multiplexing Dynamic energy, 49, 171, 193 Dynamic power, 24 26, 121, 162, 163, 178, 183, 192, 193, 212, 213, 215, 251 Dynamic voltage and frequency scaling (DVFS), 21, 25, 26, 201 E Early ejection, 100 Early wakeup methods, 22, 28, 31, 32, 35, 37, 39 Electrical to optical conversion (EO), 223 Electro-magnetic wave (EM), 258, 259, 264 Electro-optic modulators, 228 Encoded index, 156 158 Encoding latency, 157, 162 Encoding methods, 73 Encoding status, 157 Encoding table, 152, 156, 158 160, 168 171 End-to-end latency/delay, 183, 192, 194 Energy-efficient link design, 45 Energy model, 121 Error resilience, 75 Express cube, 171 F Fault model, 121 FDMA. See Frequency-division multipleaccess Field programmable resource array (FPRA), 114 FIFO buffers, 23, 24, 35, 116, 144, 145 Fine-grained power gating, 22, 26 31, 34 37, 40 42 First-come first-serve (FCFS) scheduler, 158 Flit assembly, 157 Flit fragmentation, 155 156 Flit sequence identifier, 157 Flit size, 36, 155, 156, 186 Floorplan, 201, 202, 204 206, 210, 213, 214 Flow control, 10, 12, 75, 77, 115, 155, 156, 188, 236, 250 FPC. See Frequent pattern compression FPRA. See Field programmable resource array Frequency converter, 202, 203, 211 215, 217 220 Frequency-division multiple-access (FDMA), 259 261 Frequency synchronizer, 203, 212 Frequent pattern compression (FPC), 153, 164 Frequent value coding (FV), 47 48 Full-swing wires, 232, 233 Full system simulator, 247 G GALS. See Globally asynchronous locally synchronous Gate-level model, 121 General execution-driven multiprocessor simulator (GEMS), 36, 162 General purpose domain, 135 Global clock, 72, 73, 96, 97 Globally asynchronous locally synchronous (GALS), 52, 76, 95, 98, 200 202 evolution, 96 Global wires, 59, 60, 156, 163, 201, 224, 225, 233 Gray code, 48, 49 Guaranteed service network, 97 4G wireless modem, 176 H Hamming distance, 90 Handshake interconnect, 74 Handshake interface, 74 Handshake protocol, 52, 76, 80, 88, 103 Header flit, 23, 24, 117, 119, 137, 188, 213 Head of line (HOL) blocking, 23, 155 Heterogeneous NoC, 6, 7, 256 Heterogeneous systems, 3, 256 Hierarchical NoC, 6, 7, 202 High-radix router, 162, 163, 168 High-radix topology, 152 History-based voltage scaling, 53 Homogeneous tiles, 155 Hop count, 116, 157, 166, 168, 184 Hot-spot regions, 116 Huffman encoding, 164 Hybrid network, 7, 19 Hypercube topology, 118 I Index size, 156 In-order delivery, 158 Input channel, 32, 33, 123, 131 Intelligent router, 152
284 Index Intermediate wires, 224, 225 Inter-wire capacitance, 163 Intra-die variations, 45, 73 Irregular networks, 120 ITRS, 224, 230, 239, 248, 257, 258, 273 J Jamb latch synchronizer, 99 L Lasers, 228, 229, 231, 233, 243, 246, 248 Latency constraints, 176, 180, 183, 185, 186, 194, 206, 208 210, 215 hiding techniques, 171 jitter, 122 requirement, 27, 178, 179, 183, 185, 192 Leakage current, 22, 26, 29, 60, 64, 233 Leakage power, 21, 22, 25 28, 31, 34, 35, 39 41, 50, 60, 61, 75, 163, 199, 200, 215, 220, 232, 248, 251 LEDR. See Level-encoded dual-rail LETS. See Level-encoded transition-signal Level converter, 49, 51 Level-encoded dual-rail (LEDR), 86, 91, 92 Level-encoded transition-signal (LETS), 86, 91, 92 Level shifter, 57, 63 Level signalling, 79 Link bandwidth, 24, 114, 142, 192 capacity, 178, 182, 184 186, 191 193 controller, 75 model, 59, 78 power, 50 52, 60, 163, 168, 217 swing voltage, 46, 49, 53, 54, 57, 60, 66 Local wires, 224 Logical partitioning, 211 213, 216 Logic synthesis, 102 103, 176 Long wires, 92, 93, 251, 278 Lookahead methods, 34, 58, 64, 66 Lookahead routing, 155 Lookahead transmitter, 55 58 Low-radix router, 163 Low swing drivers, 49, 233 Low swing interconnect, 54, 267 Low swing receivers, 49 Low swing signaling, 49 50, 265 Low swing techniques, 49 Low swing wires, 232, 233 LZW compression, 164 M Manhattan distance, 157 Mapping, 103, 122, 135, 176 178, 181 186, 188, 192 194 function, 123 125, 128 Maximum bandwidth, 136, 179, 206 Mean time between failures (MTBF), 99 Mesh, 2 8, 10, 15, 33, 36, 52, 53, 102, 121, 125, 132 143, 152, 154, 155, 162, 163, 171, 183, 224, 226, 248 251, 257, 272 274 topology, 114, 118, 120, 131, 140, 142, 144, 147, 179, 182, 256, 278 Mesochronous synchronizer, 97, 219 Metal resources, 152, 156 Metal wires, 78, 276 Min-cut partitioning, 207, 208 Minimal routing, 117, 124, 131 Modulator, 226 231, 236, 244, 246, 266, 269 Module mapping, 176, 196 Multiband communications, 260, 262 Multiband RF-interconnect, 256, 258 260, 263, 268 Multicast addressing, 76 Multicast support, 259 Multicore processors, 7, 227, 239 Multi-flit packet, 169 Multiple writer single reader (MWSR), 235 236 Multi-threaded program, 164 Multi-voltage system, 58 Mutual exclusion (MUTEX) element, 90, 101, 102 N Nanophotonic NOC, 225, 229, 252 Network parameters, 36, 168 simulator, 162, 247, 248 status information, 117, 144 Network interface (NI), 33, 34, 42, 96, 119, 155 156, 162, 170, 203, 205, 207, 240, 242 N -of- M code, 84 Non-homogeneous topology, 119 Non-minimal routing, 119 Nonput channel, 81 O Oblivious routing, 116 1118 Odd-even routing, 139, 144 147 Off-chip memory controller, 152
Index 285 1-of-N encoding, 83, 92 On-chip bandwidth, 224, 227 On-chip cache, 152 One-hot encoding, 47, 83, 92 On-off keying (OOK), 228, 229 Operand isolation, 21, 24, 25 Operating frequency, 4, 25, 39, 40, 202, 205, 207, 211, 216, 217 Operating voltages, 58, 59, 63, 202, 234 Optical arbitration, 236 238 Optical barrier, 238 239 Optical communication, 225, 226, 230, 231, 244, 246 Optical data transmission, 227 Optical interconnect, 225 227, 233 236, 240, 245, 273 277 Optical layer, 231 Optical NoC, 225, 226 Optical to electrical (OE) conversion, 234 Optical token channel, 237 Optical transmission, 225 Orion, 162 Output channel, 32, 117, 119, 123, 131 P Packet latency, 114, 168 177, 243, 272 length, 157, 164, 238 width, 189 Packet injection rate (pir), 136, 137, 139, 141 143 Packet-switched arbitration, 7 9, 15 Packet-switched network, 3 19, 96, 100 Parallel link, 94 95 Pausable clocking, 98 Payload size, 154 Peak performance, 26 Peak power, 17, 47, 60 Petrify, 102 106 Petri nets, 71, 77, 78, 88, 93, 94, 102, 103 Phase encoding, 89 90 2-Phase handshake, 80, 92 4-Phase handshake, 80, 82 2-Phase signalling, 88 Physical channels, 22, 23, 27, 28, 40, 163, 227 Pipeline bus, 4 Pir. See Packet injection rate Place & route, 179, 182, 193 PLL, 26, 262, 265 Point-to-point latency/delay, 178, 183 Point-to-point link, 72, 100 Power domains, 26 32, 34, 35, 37, 40, 41 gating, 21 42, 75, 200 management, 22, 26, 28 model, 163 Private table scheme, 158 160, 171 Processing element (PE), 154, 155, 158 160, 170, 171, 231 Pull channel, 81, 88 Pulsed transmission, 51 52 Pulse signalling, 88 Push channel, 81, 82, 87, 88 Q Quality of service, 97, 177 Quasi-resonant interconnect, 52 R Race conditions, 73 RAM cells, 170 Reliability, 53, 54, 58, 65, 91, 234 Repeater insertion, 46, 49, 50, 52, 66 Replacement policy, 158, 164, 165 Request message, 155 Response message, 155 Return-to-zero (RTZ), 74, 76, 80 Ring channel, 76, 85 topology, 4 Round-robin priority, 10, 12, 13 Routers architecture, 22 25, 40, 115, 143 144, 146, 188 190 delay, 157 energy, 121, 157 Routing algorithm, 97, 100, 112 148, 158, 171, 182, 225 Routing function, 115 119, 123, 124, 126 133, 144 146 Routing logic, 100, 119 120, 145 Routing scheme, 7, 115, 119 Routing table, 23, 115, 116, 119, 125, 128, 131 133, 144, 145, 147 Routing table compression, 131 133, 145 RTZ. See Return-to-zero Run-time power management, 22 Run-tme power gating, 21 42 S Safety margins, 53, 73, 87 Saturation point, 137, 139, 141, 142
286 Index Segmented-based routing, 118 Segmented bus, 5, 179 Selection function, 117 119, 144 policy, 117, 137, 139, 144 strategy, 117, 119 Self-synchronous protocol, 89 Self-timed FIFO, 76 Self-timed interface, 76, 103 Self-timed router, 76 Self-timed system, 76 Serialization latency, 157 Serial link, 94 95 Shared bus, 4, 76, 175 Shared memory system, 155 Shared table management, 161 Shared table scheme, 152, 158, 160, 166, 168, 171, 172 Shutdown mechanism, 202 Signal integrity, 226 Signalling schemes, 72, 80, 88 Signal pulses, 79 Signal to noise ratio (SNR), 259, 264, 265 Signal transition graphs (STG), 102 106 Silicon photonics, 227, 228 Simics, 36, 162 Single event upsets (SEU), 89 92 Single-flit packet, 164, 169 Single-threaded program, 164 Single-track signalling, 88 Single transition codes, 86 Single writer multiple reader (SWMR), 235, 236 Skewed repeaters, 50 Sleep transistors, 200 Slot generation circuit, 11 Smart routing, 118 SNUCA-CMP, 154, 155, 162 164, 166 170, 172 Soft-error tollerance, 71 Source routing, 23, 115, 119 Speculative switch allocation, 155 Speed-independent circuits, 73 Sperner encoding, 76 SPLASH-2, 31, 32, 37, 38, 247, 249, 250 Standby power, 25, 27 Static energy, 171, 193, 234 Static power, 22, 52, 75, 121, 183, 193 STG. See Signal transition graphs Streaming circuits, 15, 18 Supply voltage, 7, 18, 25, 26, 45, 46, 49, 51, 53, 54, 64, 256 Switch controller, 100 Switching activity, 16, 24, 25, 121, 168, 211 Switching fabric, 100 Switching power, 14, 21 Switching technique, 115, 144 SWMR. See Single writer multiple reader Synchronizers, 97 99, 106, 212, 219 Synchronous design, 91, 102, 203, 217 Synchronous island, 98 Synchronous logic, 73 Synchronous pipeline, 92 Syntax-driven design, 102, 103 T Table-based data compression, 153, 154, 172 Table-based routing, 147 Table management protocol, 160, 172 Task mapping phase, 122 Thermal noise, 264, 265, 278 Throughput jitter, 122 Through silicon vias (TSVs), 204, 210, 211, 220, 231, 239, 246 TILED-CMP, 155, 162 164, 166 170, 172 Timing requirements, 64, 176, 179, 181 183, 185, 186, 192 Token based approach, 73 Token-based protocol, 76 Token channel, 237, 238, 242 Token slot, 237, 238 Topology graph, 123 126, 128, 133 synthesis, 201, 205 Topology-agnostic routing, 118 Torus, 5 topology, 224 Total capacity, 185 187 Transceiver architecture, 264, 278 Transition detection, 54 56 Transition detection circuit, 54 56, 58 Transition signalling, 79 Trasmission-lines (TLs), 256, 259 261, 264 269, 272, 276 278 TRIMOSBUS, 76 TSVs. See Through silicon vias Two inverter link driver, 60 V Validity bit, 78 Value locality, 153, 160 Value locality buffer (VLB), 161, 166, 170 Value size, 156, 170 Virtual channels (VCs), 5, 27 37, 39 41, 100, 118, 121, 136, 155, 162, 163, 169, 184, 186 193 router, 22 25
Index 287 Virtual cut-through, 116 Voltage control circuits, 55 Voltage islands (VIs), 200 219 W Wakeup control methods, 31 35 Wakeup control network, 33 Wakeup latency, 22, 26 32, 34, 35, 37 41 Wakeup signals, 33, 34, 37 Waveguides, 226 231, 233, 236, 238 240, 243, 244, 246, 252 Wavelenght division multiplexing (WDM), 226 Wide channels, 152, 163 Wire capacitance (c w ), 163, 225 Wire delay (T w ), 34, 37, 74, 88, 92, 157, 163, 201, 232, 233 Wire-substrate capacitance (c s ), 163 Wormhole router, 22, 116, 248 switching, 115 117, 136, 144, 155, 157, 182, 186 Worst-case design, 53 X XY routing, 122, 139