TIMA Lab. Research Reports

Transcription

1 ISSN TIMA Lab. Research Reports TIMA Laboratory, 46 avenue Félix Viallet, Grenoble France

2 Session Hop Topics for SoC Design Asynchronous System Design Prof. Marc RENAUDIN TIMA, Grenoble, France 1

3 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 2

4 Asynchronous Circuits Principles Data-flow instead of control-flow If rising_edge of clock then send output = f(inputs) Else output remains unchanged End if Wait for inputs valid output = f(inputs) Complete input transactions Wait for output ready to receive send output Complete output transaction 3

5 Asynchronous Circuits Principles At the scale of an individual hardware module - every clock cycles trigger the computation - data availability trigger the computation Global Clock distribution replaced by local channels (handshaking) 4

6 Asynchronous Circuits Principles Composing hardware modules Instr Op1 Op2 Mux M1 DeMux Out M2 Irregularities in Data-streams Irregularities in latencies 5

7 Asynchronous Circuits Principles Synchronous circuits : balance the pipelines (worst case approach) Instr Op1 Op2 clk clk clk Out clk clk Circuit : add latency, increase power consumption Design Meth : need to know the state of the whole architecture in each cycle What happen if the system is very complex? Difficult to exploit input data stream irregularities 6

8 Asynchronous Circuits Principles Asynchronous circuits : ensure data flows Instr Op1 Op2 Out Circuit : latency is always minimum, as well as power consumption Design Meth : no need to know the state of the whole architecture pipelining do preserve functional correctness Easy to compose a complex system using simple modules Free to exploit input data stream irregularities 7

9 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 8

10 Asynchronous circuit styles Request Emitter Data Acknowledge Receiver Unified asynchronous interface Two basic rules : the emitter issues a request when a data is valid the receiver issues an acknowledge when the data is processed Control and data are encoded (together or not) A lot of handshake protocols Several hardware implementation fi Trade-offs 9

11 Asynchronous circuit styles Asynchronous circuits => delay insensitivity No global clock = no global timing assumption Sequencing is based on Handshaking => Hazard free logic is required Delay insensitive circuits Quasi delay insensitive circuits Speed independent circuits Micropipeline Huffman / Burst-mode circuits Robustness & Complexity are decreasing : more timing assumptions 10

12 Asynchronous circuit styles Micropipeline (a bit conservative!) Request Data Reg Ctrl Log. Reg Ctrl Log. Reg Ctrl Acknowledge time is discrete combinational logic is simple communication channels (handshake based) worst case approach locally Local timing assumptions 11

13 Asynchronous circuit styles Quasi Delay Insensitive & Speed Independent (more aggressive) => hazard free control logic & hazard free data-paths Data Reg HFL Reg HFL Reg Acknowledge time is no longer discrete hazard free combinational logic handshake based communications mean time approach No timing assumption 12

14 Asynchronous circuit styles Pros Cons Delay insensitive Fast Low power with some design effort Self-testable with certain logic style Larger area QDI Synthesis of data-paths is complex Pros Cons Micropipeline Low power with some design effort Low overhead Synthesis of data-path is performed using commercial tools Not delay insensitive Not very fast Some parts are difficult to test (delay fault) 13

15 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 14

16 Design methodology Graph based (Petri-Nets) Signal Transition Graphs Burst-mode specification Language based (CSP based) Tangram (Philips) Balsa (University of Manchester) Tast (Tima) Small controllers Complex circuits ACiD-WG : " Design, Automation and Test for Asynchronous Circuits and Systems" 15

17 TAST : Tima Asynchronous circuit Synthesis Tools Use a high-level specification language to model circuits Enable to target different asynchronous circuit styles Enable to validate/simulate different circuit styles : synchronous and asynchronous (reusability) Make use of existing commercial CAD Tools as much as possible, and is interfaced with them. Propose a complete design flow similar to existing flow Not addressed so far : Testability Timing analysis 16

18 TAST : objectives TIMA/CIS tools perspectives : Asynchronous Circuits and Interfaces synthesis Multiple source languages (HDL, System C ) Other languages (translation) Formal Verification Internal form Analysis & Transformations Multiple hardware targets : Clock, Gated-Clock, Asynchronous (µ_pipe, QDI ) 17

19 Language for Asynchronous Circuits Modeling and Synthesis Which language? CHP as a starting point «Communicating Hardware Processes» High level behavioral specification Support for Concurrency specification Inside processes Hierarchical structural specifications Communication channels Definition Read, write and probe Other languages in the future (HDL) Environment P1 P3 P0 P2 18

20 TAST : design methodology Programs Compiler VHDL Generator Checks for synthesis Hardware Target Choice Functional VHDL Micropipeline -VHDL Gate Netlist for the control part - VHDL Data-flow for the Data-Path QDI - VHDL Gate Netlist for the whole circuit RTL Synthesis Optimization Technology mapping VHDL Co-Simulation 19

21 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 20

22 SoCs design requirements Assemble / Reuse new and existing modules Modules with very different architectures Modules activity may be very different Modules with different speed/power trade-offs Flexible on-chip communication mechanisms Low power D A Sensor C Processing B Supervision, network... Modularity and locality => reusability Get rid of global constraints (like a unique global clock) Avoid inheritance of constraints from block to block (like clock, noise, communication and synchronization mechanisms ) Do not consume when not in use 21

23 SoCs design requirements Modularity, Locality Need to Adopt the right Hardware model and the right Specification model P0 Asynchronous Logic and Communicating Concurrent Processes P1 P3 P2 22

24 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 23

25 Modularity and Locality Communication through channels (no clock) Protocols are in charge of interfacing modules => the design of different modules is not inter-dependent Design problems are solved locally inside each module (architecture, speed, power, back-end issues ) Building a complex architecture using modules implementing handshake communication protocols is easy Stand-by mode is free Channels are used to trigger modules processing Go from zero to maximum activity immediately, on request 24

26 Modularity and Locality Speed and functionality issues are solved separately Within a module For inter-module communications P0 = [ A? x......] P1 = [ A! y......] - Pipelining is preserving functional correctness in an asynchronous circuit => Performance optimization do not change the functionality 25

27 Modularity and Locality Circuit architecture D, Ctrl N stages P stages => Locality : global state knowledge is not required! 26

28 Modularity and Locality Thanks to asynchronous circuits Provide a complete framework for jointly implementing communication channels and functions (hardware communicating processes) SoCs design is then easier : Distributed control (protocol implementation) Delay insensitive communications between modules Modules are independent from each other in terms of : Functionality (global state not known) Speed (maximum speed) Activity (power) Noise (uncorrelated current consumption) Scalability Modularity Reusability Scalability 27

29 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 28

30 On-chip Communication Systems Long wires Insert clocked registers Multiple Clock Domains (GALS) => Metastability may occur at clock domain boundaries Existing solutions Control the Mean Time Between Failure (MTBF) Non adaptive synchronization Adaptive synchronization Avoiding metastability Stretchable clocks Fully asynchronous (GALA) Issues : reliability and latency Probability of error is not zero Probability of error is zero 29

31 On-chip Communication Systems GALA : fully asynchronous circuits Modeling/Synthesis of arbitration problems from communicating processes to gates requires two extra basic cells : ME and Sync Safe and Fast channels may be independently processed speed only depends of the complexity of the arbitration scheme Low power data driven Area no data buffering required complexity depends on the asynchronous logic style used 30

32 Asynchronous On-Chip Busses design Fully asynchronous circuits use DI codes which have nice properties for on-chip busses design One-of-N (4-phase protocols / 2-phase protocols) Low power Cross-talk is reduced Speed is increased Electrical buffering and pipelining at the same time Safe, fast and low-power arbiters can be designed Area is about the same 31

33 Asynchronous On-Chip Busses design 1-of-4 DI code energy efficiency Wires/bit Transitions/bit single rail 1 1/2 on average dual-rail 4-phase 2 2 dual-rail 2-phase of-4 4-phase of-4 2-phase 2 1/2 Same Wire/bit than dual-rail code but more energy efficient 32

34 Asynchronous On-Chip Busses design DI codes for cross-talk reduction Minimum spacing within digits Larger spacing between digits to prevent crosstalk Minimum spacing within digits We know where cross-talk is likely to happen Area overhead is small even if the number of wires is doubled Acknowledge signals may be used as spacers 33

35 Asynchronous On-Chip Busses design DI code for long wires routing Repeaters perform electrical buffering and pipelining at the same time Much faster than Safe, fast and low-power arbiters can be designed 34

36 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 35

37 Automatic performance regulation Computation-power controlled systems : E = a.fcv² Asynchronous System VDD DC/DC Converter fi Minimum energy computation Inputs Control FIFO Processing FIFO Dynamic regulation of the power supply with respect to the processing power required. (Philips Research, DCC) Outputs Exploit : - Processing and data have irregular nature - a breakdown with respect to the synchronous approach 36

38 Automatic performance regulation Power supply controlled systems Processing power is limited by the power budget available Maximum performance delivered with the available power received Voltage Current Activity = processing power 37

39 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 38

40 Noise Measurements performed with "MICA" an asynchronous QDI 8-bit microcontroller Current profile Courant de consommation moyen de MICA Amplitude en A ma average current ma amplitude variations Mean power consumption is lower Smaller current peaks, EM emission is lower Temps en ns (fréquence d échantillonnage 25 Ghz; Nombre de points 15000) 39

41 Noise Measurements performed with "MICA" an asynchronous QDI 8-bit microcontroller Current spectrum 8 x 10-5 Spectre de frequence de MICA Max = x Spectre de frequence de MICA 6 6 Amplitude du spectre 4 Amplitude du spectre frequence en Hz x 10 9 (fréquence d échantillonnage 25 Ghz; Nombre de points 15000) frequence en Hz x to 12.5 GHz 16 MHz 0 to 0.5 GHz 40

42 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 41

43 Security MEDEA+ project (A302) Enhanced Smartcard Platform for Accessing Securely Services of the Information Society Goals : provide an innovative design technique and associated CAD tools to improve security and power consumption uncorrelated data processing and electric-magnetic observations Contributions : study asynchronous logic to figure out the best asynchronous circuit style to improve security (signature) develop the corresponding CAD tools to generate secure circuits against timing and power analysis attacks 42

44 Security Galois-field Multiplier Inputs = FF Inputs = 00 Architecture and cells are designed so that input data are processed using an equal number of electrical transitions 43

45 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoCprototype Conclusion 44

46 Contact less Smart-Card Chip "SoC" for Contact less Smart-Card Power reception system (on-chip coil) ISO B std compliant 8-bit CISC Asynchronous Micro controller designed with standard cells (Mica) Rom Rams Collaboration with France Telecom/R&D Cmos 0.25 µm STMicroelectronics [IEEE-JSSC July 2001] 45

47 Contact less Smart-Card Chip Asynchronous Logic relaxed Design constraints Not sensitive to supply voltage variations Power reception system (capacitances area, voltage regulation) Lower current peaks The Micro-controller can be running during the communications without disturbing the load modulation. Maximum processing power delivered according to the power received Collaboration with France Telecom/R&D Cmos 0.25 µm STMicroelectronics [IEEE-JSSC July 2001] 46

48 Mica : an 8-bit CISC QDI Asynchronous µc 1-of-4 DI codes for arith. and reg. 1-of-n DI codes for the control Complexity transistors 1 M transistors with memories 13 mm² with pads (prototype) PGA120 package for the prototype Test BIST (approx. 300 instr) functional at 1 er silicon between 3v et 0.65 v 24 Mips / V 4,3 Mips / 800 1V Mips 35,0 30,0 25,0 20,0 15,0 10,0 5,0 0,0 Mips 1 1,5 2 2,5 3 3,5 Supply Power(mW) 100,0 Supply(V) Mips Core Current (ma) Power(mW) Mips/Watt 1 4,3 0,8 0,8 5503,6 1,5 11,9 3,1 4,7 2560,2 2 18,6 6,7 13,3 1398,0 2,5 23,8 11,2 28,0 850,3 3 27,8 16,3 48,9 568,1 3,5 31,3 22,0 77,0 405,8 80,0 60,0 40,0 20,0 0,0 POwer (mw) 47

49 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 48

50 Conclusion Channel-based SoCs instead of clock-based Delay-insensitive instead of timing-driven modularity, locality, scalability => reusability design time => time to market Tools, tools, tools needed! 49

51 Conclusion GALS is a intermediate/short term solution? When clock frequency increases Number of time-zones/clock-domains increases MTBF decreases Noise increases GALS overheads increases, reliability issue Fully asynchronous / GALA SoCs is the future? Reduce the clock to a common resource of a SoC, only used to measure time 50

52 Session Hop Topics for SoC Design Asynchronous System Design Prof. Marc RENAUDIN TIMA, Grenoble, France 1

53 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 2

54 Asynchronous Circuits Principles Data-flow instead of control-flow If rising_edge of clock then send output = f(inputs) Else output remains unchanged End if Wait for inputs valid output = f(inputs) Complete input transactions Wait for output ready to receive send output Complete output transaction 3

55 Asynchronous Circuits Principles At the scale of an individual hardware module - every clock cycles trigger the computation - data availability trigger the computation Global Clock distribution replaced by local channels (handshaking) 4

56 Asynchronous Circuits Principles Composing hardware modules Instr Op1 Op2 Mux M1 DeMux Out M2 Irregularities in Data-streams Irregularities in latencies 5

57 Asynchronous Circuits Principles Synchronous circuits : balance the pipelines (worst case approach) Instr Op1 Op2 clk clk clk Out clk clk Circuit : add latency, increase power consumption Design Meth : need to know the state of the whole architecture in each cycle What happen if the system is very complex? Difficult to exploit input data stream irregularities 6

58 Asynchronous Circuits Principles Asynchronous circuits : ensure data flows Instr Op1 Op2 Out Circuit : latency is always minimum, as well as power consumption Design Meth : no need to know the state of the whole architecture pipelining do preserve functional correctness Easy to compose a complex system using simple modules Free to exploit input data stream irregularities 7

59 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 8

60 Asynchronous circuit styles Request Emitter Data Acknowledge Receiver Unified asynchronous interface Two basic rules : the emitter issues a request when a data is valid the receiver issues an acknowledge when the data is processed Control and data are encoded (together or not) A lot of handshake protocols Several hardware implementation fi Trade-offs 9

61 Asynchronous circuit styles Asynchronous circuits => delay insensitivity No global clock = no global timing assumption Sequencing is based on Handshaking => Hazard free logic is required Delay insensitive circuits Quasi delay insensitive circuits Speed independent circuits Micropipeline Huffman / Burst-mode circuits Robustness & Complexity are decreasing : more timing assumptions 10

62 Asynchronous circuit styles Micropipeline (a bit conservative!) Request Data Reg Ctrl Log. Reg Ctrl Log. Reg Ctrl Acknowledge time is discrete combinational logic is simple communication channels (handshake based) worst case approach locally Local timing assumptions 11

63 Asynchronous circuit styles Quasi Delay Insensitive & Speed Independent (more aggressive) => hazard free control logic & hazard free data-paths Data Reg HFL Reg HFL Reg Acknowledge time is no longer discrete hazard free combinational logic handshake based communications mean time approach No timing assumption 12

64 Asynchronous circuit styles Pros Cons Delay insensitive Fast Low power with some design effort Self-testable with certain logic style Larger area QDI Synthesis of data-paths is complex Pros Cons Micropipeline Low power with some design effort Low overhead Synthesis of data-path is performed using commercial tools Not delay insensitive Not very fast Some parts are difficult to test (delay fault) 13

65 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 14

66 Design methodology Graph based (Petri-Nets) Signal Transition Graphs Burst-mode specification Language based (CSP based) Tangram (Philips) Balsa (University of Manchester) Tast (Tima) Small controllers Complex circuits ACiD-WG : " Design, Automation and Test for Asynchronous Circuits and Systems" 15

67 TAST : Tima Asynchronous circuit Synthesis Tools Use a high-level specification language to model circuits Enable to target different asynchronous circuit styles Enable to validate/simulate different circuit styles : synchronous and asynchronous (reusability) Make use of existing commercial CAD Tools as much as possible, and is interfaced with them. Propose a complete design flow similar to existing flow Not addressed so far : Testability Timing analysis 16

68 TAST : objectives TIMA/CIS tools perspectives : Asynchronous Circuits and Interfaces synthesis Multiple source languages (HDL, System C ) Other languages (translation) Formal Verification Internal form Analysis & Transformations Multiple hardware targets : Clock, Gated-Clock, Asynchronous (µ_pipe, QDI ) 17

69 Language for Asynchronous Circuits Modeling and Synthesis Which language? CHP as a starting point «Communicating Hardware Processes» High level behavioral specification Support for Concurrency specification Inside processes Hierarchical structural specifications Communication channels Definition Read, write and probe Other languages in the future (HDL) Environment P1 P3 P0 P2 18

70 TAST : design methodology Programs Compiler VHDL Generator Checks for synthesis Hardware Target Choice Functional VHDL Micropipeline -VHDL Gate Netlist for the control part - VHDL Data-flow for the Data-Path QDI - VHDL Gate Netlist for the whole circuit RTL Synthesis Optimization Technology mapping VHDL Co-Simulation 19

71 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 20

72 SoCs design requirements Assemble / Reuse new and existing modules Modules with very different architectures Modules activity may be very different Modules with different speed/power trade-offs Flexible on-chip communication mechanisms Low power D A Sensor C Processing B Supervision, network... Modularity and locality => reusability Get rid of global constraints (like a unique global clock) Avoid inheritance of constraints from block to block (like clock, noise, communication and synchronization mechanisms ) Do not consume when not in use 21

73 SoCs design requirements Modularity, Locality Need to Adopt the right Hardware model and the right Specification model P0 Asynchronous Logic and Communicating Concurrent Processes P1 P3 P2 22

74 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 23

75 Modularity and Locality Communication through channels (no clock) Protocols are in charge of interfacing modules => the design of different modules is not inter-dependent Design problems are solved locally inside each module (architecture, speed, power, back-end issues ) Building a complex architecture using modules implementing handshake communication protocols is easy Stand-by mode is free Channels are used to trigger modules processing Go from zero to maximum activity immediately, on request 24

76 Modularity and Locality Speed and functionality issues are solved separately Within a module For inter-module communications P0 = [ A? x......] P1 = [ A! y......] - Pipelining is preserving functional correctness in an asynchronous circuit => Performance optimization do not change the functionality 25

77 Modularity and Locality Circuit architecture D, Ctrl N stages P stages => Locality : global state knowledge is not required! 26

78 Modularity and Locality Thanks to asynchronous circuits Provide a complete framework for jointly implementing communication channels and functions (hardware communicating processes) SoCs design is then easier : Distributed control (protocol implementation) Delay insensitive communications between modules Modules are independent from each other in terms of : Functionality (global state not known) Speed (maximum speed) Activity (power) Noise (uncorrelated current consumption) Scalability Modularity Reusability Scalability 27

79 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 28

80 On-chip Communication Systems Long wires Insert clocked registers Multiple Clock Domains (GALS) => Metastability may occur at clock domain boundaries Existing solutions Control the Mean Time Between Failure (MTBF) Non adaptive synchronization Adaptive synchronization Avoiding metastability Stretchable clocks Fully asynchronous (GALA) Issues : reliability and latency Probability of error is not zero Probability of error is zero 29

81 On-chip Communication Systems GALA : fully asynchronous circuits Modeling/Synthesis of arbitration problems from communicating processes to gates requires two extra basic cells : ME and Sync Safe and Fast channels may be independently processed speed only depends of the complexity of the arbitration scheme Low power data driven Area no data buffering required complexity depends on the asynchronous logic style used 30

82 Asynchronous On-Chip Busses design Fully asynchronous circuits use DI codes which have nice properties for on-chip busses design One-of-N (4-phase protocols / 2-phase protocols) Low power Cross-talk is reduced Speed is increased Electrical buffering and pipelining at the same time Safe, fast and low-power arbiters can be designed Area is about the same 31

83 Asynchronous On-Chip Busses design 1-of-4 DI code energy efficiency Wires/bit Transitions/bit single rail 1 1/2 on average dual-rail 4-phase 2 2 dual-rail 2-phase of-4 4-phase of-4 2-phase 2 1/2 Same Wire/bit than dual-rail code but more energy efficient 32

84 Asynchronous On-Chip Busses design DI codes for cross-talk reduction Minimum spacing within digits Larger spacing between digits to prevent crosstalk Minimum spacing within digits We know where cross-talk is likely to happen Area overhead is small even if the number of wires is doubled Acknowledge signals may be used as spacers 33

85 Asynchronous On-Chip Busses design DI code for long wires routing Repeaters perform electrical buffering and pipelining at the same time Much faster than Safe, fast and low-power arbiters can be designed 34

86 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 35

87 Automatic performance regulation Computation-power controlled systems : E = a.fcv² Asynchronous System VDD DC/DC Converter fi Minimum energy computation Inputs Control FIFO Processing FIFO Dynamic regulation of the power supply with respect to the processing power required. (Philips Research, DCC) Outputs Exploit : - Processing and data have irregular nature - a breakdown with respect to the synchronous approach 36

88 Automatic performance regulation Power supply controlled systems Processing power is limited by the power budget available Maximum performance delivered with the available power received Voltage Current Activity = processing power 37

89 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 38

90 Noise Measurements performed with "MICA" an asynchronous QDI 8-bit microcontroller Current profile Courant de consommation moyen de MICA Amplitude en A ma average current ma amplitude variations Mean power consumption is lower Smaller current peaks, EM emission is lower Temps en ns (fréquence d échantillonnage 25 Ghz; Nombre de points 15000) 39

91 Noise Measurements performed with "MICA" an asynchronous QDI 8-bit microcontroller Current spectrum 8 x 10-5 Spectre de frequence de MICA Max = x Spectre de frequence de MICA 6 6 Amplitude du spectre 4 Amplitude du spectre frequence en Hz x 10 9 (fréquence d échantillonnage 25 Ghz; Nombre de points 15000) frequence en Hz x to 12.5 GHz 16 MHz 0 to 0.5 GHz 40

92 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 41

93 Security MEDEA+ project (A302) Enhanced Smartcard Platform for Accessing Securely Services of the Information Society Goals : provide an innovative design technique and associated CAD tools to improve security and power consumption uncorrelated data processing and electric-magnetic observations Contributions : study asynchronous logic to figure out the best asynchronous circuit style to improve security (signature) develop the corresponding CAD tools to generate secure circuits against timing and power analysis attacks 42

94 Security Galois-field Multiplier Inputs = FF Inputs = 00 Architecture and cells are designed so that input data are processed using an equal number of electrical transitions 43

95 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoCprototype Conclusion 44

96 Contact less Smart-Card Chip "SoC" for Contact less Smart-Card Power reception system (on-chip coil) ISO B std compliant 8-bit CISC Asynchronous Micro controller designed with standard cells (Mica) Rom Rams Collaboration with France Telecom/R&D Cmos 0.25 µm STMicroelectronics [IEEE-JSSC July 2001] 45

97 Contact less Smart-Card Chip Asynchronous Logic relaxed Design constraints Not sensitive to supply voltage variations Power reception system (capacitances area, voltage regulation) Lower current peaks The Micro-controller can be running during the communications without disturbing the load modulation. Maximum processing power delivered according to the power received Collaboration with France Telecom/R&D Cmos 0.25 µm STMicroelectronics [IEEE-JSSC July 2001] 46

98 Mica : an 8-bit CISC QDI Asynchronous µc 1-of-4 DI codes for arith. and reg. 1-of-n DI codes for the control Complexity transistors 1 M transistors with memories 13 mm² with pads (prototype) PGA120 package for the prototype Test BIST (approx. 300 instr) functional at 1 er silicon between 3v et 0.65 v 24 Mips / V 4,3 Mips / 800 1V Mips 35,0 30,0 25,0 20,0 15,0 10,0 5,0 0,0 Mips 1 1,5 2 2,5 3 3,5 Supply Power(mW) 100,0 Supply(V) Mips Core Current (ma) Power(mW) Mips/Watt 1 4,3 0,8 0,8 5503,6 1,5 11,9 3,1 4,7 2560,2 2 18,6 6,7 13,3 1398,0 2,5 23,8 11,2 28,0 850,3 3 27,8 16,3 48,9 568,1 3,5 31,3 22,0 77,0 405,8 80,0 60,0 40,0 20,0 0,0 POwer (mw) 47

99 Outline Asynchronous technology in a few words Asynchronous circuit principles Circuit styles Design methodology How does it make SoC design easier? SoC design requirements Modularity and locality On-Chip communication systems Automatic performance regulation Noise Security An asynchronous SoC Conclusion 48

100 Conclusion Channel-based SoCs instead of clock-based Delay-insensitive instead of timing-driven modularity, locality, scalability => reusability design time => time to market Tools, tools, tools needed! 49

101 Conclusion GALS is a intermediate/short term solution? When clock frequency increases Number of time-zones/clock-domains increases MTBF decreases Noise increases GALS overheads increases, reliability issue Fully asynchronous / GALA SoCs is the future? Reduce the clock to a common resource of a SoC, only used to measure time 50