Design and Test Solutions for Networks-on-Chip. Jin-Ho Ahn Hoseo University

Transcription

1 Design and Test Solutions for Networks-on-Chip Jin-Ho Ahn Hoseo University

2 Topics Introduction NoC Basics NoC-elated esearch Topics NoC Design Procedure Case Studies of eal Applications NoC-Based SoC Testing Issues Conclusions 2

3 SoC: Core of Digital Convergence 3

4 SoC Components Processing unit On-chip memory H/W accelerator I/O device controllers (peripherals) Interconnection structure S3C2510 (Samsung) 4

5 Future SoCs Philips Viper2 130 nm 50M trans. 1 MIPS 2 Trimedia 60 IP blocks 250 AMs In 45 nm, up to 10x on a single chip 5

6 On-Chip Interconnect Evolution core core core core core core core core core core Direct/Indirect network core core core core core Bridge core core core core core core Shared Bus Hierarchy or Bridged Bus Network Based (Example) AMBA Case Complexity ASB AHB AXI AHB ML?? Scalability Predictability 6

7 Wire Design in Sub-100 nm Tech. 65nm low-power library very high frequencies or very long links infeasible 7

8 Networks-on-Chip NoC (Networks-on-Chip) An evolution of on-chip bus interconnect technology Interconnection model implemented on a chip in the form of a micro-network Borrow models, techniques, and tools from the computer network design field and apply them to SoC design 8

9 NoC Pros and Cons Pros Canonical interconnect structure Shared interconnect bandwidth Increased flexibility Cons Intra-PE interconnect delay Overhead due to interconnects 9

10 NoC Topology Core outer Mesh Octagon Butterfly Fat-Tree H-Tree 10

11 NoC-Based SoC Typical applications Complex Highly heterogeneous (component specialization) Communication intensive Tailor-made interconnects for applications NoCs are resource constrained: Power, area constraints low buffering available Large available wire bandwidth But tapping it with modular, structured design is key 11

12 Design Space for NoC-Based SoC 12

13 Category of NoC Platform Hard NoC NoC and IP positions are fixed Firm NoC NoC is pre-designed, but IP positions can be changed Soft NoC NoC components and IP positions can be changed 13

14 Topology Synthesis From multi-computer networks Designed for generalpurpose and homogenous systems egular-topology NoC 14

15 Topology Synthesis Application-Specific NoC Customized NoC for each application ASNoC brings significant performance improvements For both homogenous and heterogeneous systems Irregular-Topology NoC 15

16 egular-topology NoC Synthesis Example: XPipe 16

17 Other NoC Synthesis Irregular and hybrid-topology NoC can produce optimal topology at a given application difficult to develop EDA tools heuristic approaches are required 17

18 Design of NoC Components outer Network Interface Switching fabric Buffering scheme Flow control Arbitration 18

19 Design Issues of NoC Components NoC channel width NoC channel structure (Ex) Serial and Parallel NoC router buffer size Buffer is critical to decide the overall NoC size Needs an efficient traffic modeling NoC floorplaning maximize the performance and reduce coupling effect 19

20 NoC Communication Protocol Major objective function minimal routing path congestion avoidance deadlock or livelock uniform power consumption fault tolerant outer Application Layer Network Layer Physical Layer 20

21 Criterion for NoC outing Policy 21

22 General NoC Design Flow NoC Parameters System Level Modeling TL Generation Application Model HW/SW Co-Sim. NoC Model N Verified? Design Objective Mapping and Scheduling Y Synthesis and Formal Verification Verified? N Performance and Power Estimation Y Emulation and Layout N Objective is satisfied? Y Verified? Y To Fab. N 22

23 NoC Scheduling and Mapping NoC Characteristics Target Objective Application Model Task and PE mapping to NoC Model Feasible? Task Scheduling Satisfied? NoC Model Application mapping Assign embedded cores to the given NoC model Key of the overall performance For simplification, mapping and scheduling process are separated Mapping constraints avg. hop number power consumption etc... 23

24 e-mapping for Flexible NoC 24

25 SunFloor NoC Design Flow 25

26 Æthereal NoC Design Flow 26

27 NoC esearch Projects Nostrum at KTH Æthereal at Philips Proteo at Tampere University of Technology SPIN at UPMC/LIP6 in Paris XPipes at Bologna and Stanford Univ. Octagon at ST and UC San Diego SoCIN at UNIVALI and UFGS CHAIN at the Univ. of Manchester MANGO at the Tech. Univ. of Denmark 27

28 Case Studies of eal Applications H.264 HDTV decoder system-on-chip High-end consumer-electronics TV system-on-chip KAIST Bone series 28

29 H.264 HDTV Decoder SoC Candidate for HDTV broadcast High compression rate: 2X of MPEG2 High definition: 2 million pixel/frame 29

30 H.264 HDTV Decoder SoC ASNoC has two local networks AW is implemented based on its design documentation Positions of computation nodes are optimized The same group of computation nodes Different communication architectures ASNoC has less switches and links ASNoC AW 30

31 H.264 HDTV Decoder SoC 31

32 High-End Consumer-Electronics TV SoC The main TV chip, companion chip, and external memories. 32

33 High-End Consumer-Electronics TV SoC Architecture of companion chip with NoC 33

34 High-End Consumer-Electronics TV SoC 100MHz in a 0.13um tech. IP: 100MHz, NoC: 300MHz(1.2Gbit/sec) Area overhead: 4% Power overhead: 12% Latency overhead : 10% Simulation overhead : 15 ~ 60% Design time: 12 months by 2 designers 34

35 KAIST BONE Series BONE(Basic On-Chip Networks) Project launched in 2002 at KAIST covers circuit-level design, architectural researches and system integration on an NoC platform ( 35

36 NoC-Based SoC Testing Issues Issue Functional Core Testing NoC Communication Fabric Testing Category Wrapper Design TAM Design Test Strategy Wrapper Design TAM Design Test Strategy Status standardized wrapper definition NoC reuse under investigation (mainly related to integrated test scheduling) under investigation (standard-compliant wrapper design) NoC reuse under investigation (related to testing with multiple identical cores or distributed BIST scheme for multiple FIFOs) Integrated System Testing open problem 36

37 Generic Procedure P P M P M NI NI NI NI NI P P M P M NI NI NI NI NI NI NI NI NI NI M P M NI NI NI M P M NoC Testing Core Testing 37

38 NoC Testing Testing target router(=switch) blocks comm. wire segments Fault model comm. link: max. aggressor fault(maf) switch routing logic: SAF routing FIFO: 2-port memory mem. cell array: SAF, TF, DF, BF addressing fault: SAF other functionality faults 38

39 Packet-Based Test Data Transport Unicast mode Multicasting mode Broadcasting mode 39

40 Problems of Data Transport Unicast mode High latency, Long test time Multicasting mode High traffic load, High power consumption Broadcasting mode High traffic load, High power consumption Needs a list of all sending packets to avoid loops 40

41 NoC outer Testing outing logic small F/F and gates: full-scan uses multiple identical core testing approaches 41

42 NoC outer Testing outing buffer main problem for the router testability normal BIST is not suitable: small buffers are spread over NoC NoC buffer: 2-port memory type 42

43 NoC Wrapper Design IEEE 1500 standard wrapper assumes that TAM wires connected to a core can be assigned individually wrapper control signals can be controlled individually by an external ATE Thus, standard wrapper is unsuitable for NoC test reusing NoC as TAM 43

44 NoC Wrapper Example (1) A single test wrapper for the whole NoC 44

45 NoC Wrapper Example (2) 45

46 Conclusions Present Interconnect now dominates the design process Interconnect-aware design methodologies are needed NoC era is coming NoC is here and important for on-chip global data transfer Designing NoCs Huge design space Demonstrate good potential Application-specific networks can pay off in performance/energy But, take more time to design Efficient NoC-based SoC test is important in real cases NoC-based TAM is a prerequisite 46