High-Yield Repairing Algorithms for 2D Memory with Clustered Faults

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High-Yield Repairing Algorithms for 2D Memory with Clustered Faults Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Engineering National Changhua University of Education 2011/05/20 @CSE.NCHU

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 2 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 3 T.-C. HUANG, NCUE

Magnetic Core RAM By the early 1960 s, Magnetic Core RAM became largely universal as main memory, replacing drum memory. High-Yield Repairing Algorithms 4 T.-C. HUANG, NCUE

Magnetic Core RAM The memory cells consist of wired threaded tiny ferrite rings (cores). X and Y lines to apply the magnetic filed. Sense/Inhibit line to read the current pulse when the polarization of the magnetic field changes. High-Yield Repairing Algorithms 5 T.-C. HUANG, NCUE

Dynamic RAM (DRAM) Each bit of data is stored in a separate capacitor within an integrated circuit Volatile The highest density RAM currently available The least expensive one Moderately fast High-Yield Repairing Algorithms 6 T.-C. HUANG, NCUE

Static RAM (SRAM) Each bit is stored on four transistors that form two cross-coupled inverters Expensive Volatile Fast Low power consumption Less dense than DRAM High-Yield Repairing Algorithms 7 T.-C. HUANG, NCUE

Flash Memory Stores information in an array of memory cells made from floating-gate transistors Cheap Non-volatile Slow Enormously durable Limited endurance High-Yield Repairing Algorithms 8 T.-C. HUANG, NCUE

Phase Change Memory (PCM) Changes amorphous or crystaline phases by thermal current Emerging High density Nonversatile (source: wikipedia) High-Yield Repairing Algorithms 9 T.-C. HUANG, NCUE

Memory Families Introduction (Source: ITRS2010) High-Yield Repairing Algorithms 10 T.-C. HUANG, NCUE

Memory Families (Source: ITRS2010) High-Yield Repairing Algorithms 11 T.-C. HUANG, NCUE

Importance of Memory Repairing ITRS: Memory occupies 87% by 2014 TISA: > 33% of Semiconductor product 100% ROM, SRAM, 90% 80% 70% 60% 50% 40% 30% %Area New Logic %Area Reused Logic %Area Memory and/or DRAM 20% 10% 0% 1999 2002 2005 2008 2011 2014 High-Yield Repairing Algorithms 12 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 13 T.-C. HUANG, NCUE

Tunnel Magnetoresistance (TMR) Two thin films of altering ferromagnetic materials and an insulating spacer. Fe/MgO/Fe junctions reach over 200% decrease in electrical resistance at room temperature 600 (room temperature)-1100 (4.2 K) % TMR at junctions of CoFeB/MgO/CoFeB High-Yield Repairing Algorithms 16 T.-C. HUANG, NCUE

MRAM One of the two plates is a permanent magnet set to a particular polarity, the other's field will change to match that of an external field. High-Yield Repairing Algorithms 20 T.-C. HUANG, NCUE

Basic NOR-Type Array High-Yield Repairing Algorithms 33 T.-C. HUANG, NCUE

Basic MRAM Structures Conventional Structure with WWL + RWL Single WL Structure High-Yield Repairing Algorithms 37 T.-C. HUANG, NCUE

Fault Model Selected MJT Selected WWL Disturbed WWL High-Yield Repairing Algorithms 38 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 39 T.-C. HUANG, NCUE

Yield 良率 $USD High-Yield Repairing Algorithms 40 T.-C. HUANG, NCUE

Importance of Memory Test Without test at stage k Cost wasted: (1-Y)(P k+1 -P k ) $1 $10 $100 Rule of Tens High-Yield Repairing Algorithms 41 T.-C. HUANG, NCUE

Importance of Memory Repair When chips are very small, assume the probability of defected chip is a Y=1- a Yield ( 良率 ) 100% Seed s Model Y e AD 0 Y Murphy s Model 1 e AD AD 2 20%!!! a=ad High-Yield Repairing Algorithms 42 T.-C. HUANG, NCUE

Wafer Test Tester Prober High-Yield Repairing Algorithms 43 T.-C. HUANG, NCUE

Final Test Logic Tester Load board High-Yield Repairing Algorithms 44 T.-C. HUANG, NCUE

Typical Model of Memory Array Row Address Decoder C: Cell Array 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 Read/Write Logic D: Data A: Address Column Address Decoder High-Yield Repairing Algorithms 45 T.-C. HUANG, NCUE

Brief Introduction to March Test Zero-One Algorithm Check-board Algorithm March C Algorithm Demo using an Excel file Usually we need multiple algorithms to promote the test coverage High-Yield Repairing Algorithms 46 T.-C. HUANG, NCUE

Conventional Memory Test External memory test Typically 30M$/ATE Expensive! Clock Address Read/Write Data Go/NoGo (Pass/Fail) High-Yield Repairing Algorithms 47 T.-C. HUANG, NCUE

Conventional Memory Diagnosis External memory Diagnosis Clock Address Read/Write Data Faulty Cell Address (+ Fault Types) High-Yield Repairing Algorithms 48 T.-C. HUANG, NCUE

Pros and Cons of MRAM Low Yield Repair Low Dependability ECC High R/W Current Partitioned Power-Gating SiP 3D-IC (Source: ITRS2010) High-Yield Repairing Algorithms 49 T.-C. HUANG, NCUE

Yield and Dependability Combinatory Yield 100% 80% 60% Deterministic Faults Intermittent Errors SRAM Flash (soft errors) (disturbance) Memory Repairing Error Correction Codes 40% 20% 0% (disturbance) MRAM kb Mb Gb Tb Pb Memory Capacity per Chip High-Yield Repairing Algorithms 50 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 51 T.-C. HUANG, NCUE

Fault Models Fault (Type) Model Stuck-At Faults More Serious for MRAM Coupling Faults Neighborhood-Pattern Sensitive Faults Transition Faults Retention Faults Fault Distributing Model Line Faults Row, Column Clustered Faults What else? Hypercube Faults?? High-Yield Repairing Algorithms 52 T.-C. HUANG, NCUE

Fault Distribution Model IFA (Inductive Fault Analysis) Fault Distributor A: Address Fault Models Massive Diagnoses Row Address Decoder C: Cell Array 0 0 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 Column Address Decoder 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 1 1 0 1 Read/Write Logic D: Data ECFA (Effect-Cause Fault Analysis) High-Yield Repairing Algorithms 53 T.-C. HUANG, NCUE

Early Distribution Models Fault Types: Uniformly Random Faults Line Faults Word-Line (Row) Bit-Line (Column) Some Previous Work: CRESTA, 2000 [6] BRAVES, 2003 [3] Fault Distributor, 2007 [13] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 54 T.-C. HUANG, NCUE

Recent Distribution Models Additional Fault Type: + Clustered Faults Major Previous Work: MESP/Divided-Lines, 2010 [11] 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 55 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 56 T.-C. HUANG, NCUE

Conventional Memory Repair Laser Fusing or Flash Programming Address Decoder 1 Word Line 0 Spare Word Line Laser Fusing (Source: GSI Group) Flash Programming High-Yield Repairing Algorithms 57 T.-C. HUANG, NCUE

BISR: Built-In Self-Repair A typical BISR scheme Q D ADR MAO EMA REF ERR FCA BIRA DNE CNT Wrapper ARU Main Memory CLK POR BIST Spare Memory High-Yield Repairing Algorithms 58 T.-C. HUANG, NCUE

BISR with Spare Rows 1 1 0 0 0 1 Priority Encoder 0 1 1 BCAM: 0 1 0 Binary Content Addressable Memory High-Yield Repairing Algorithms 59 T.-C. HUANG, NCUE 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Spare Rows

Spare Rows and Columns 1 0 1 Pri. En. 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 1 1 0 0 1 1 Priority Encoder 111 High-Yield Repairing Algorithms 60 T.-C. HUANG, NCUE

Row Adr. Dec. Conventional Memory Repair BCAM-based Remap n Col. Adr. Dec. 12 11 10 Adr. m+n m m M-row N-column Memory 15 Binary CAM BCAM s Spare Row Memory 0 1 Dio 13 14 Hit High-Yield Repairing Algorithms 61 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 62 T.-C. HUANG, NCUE

Hypercubes: Two 4-Cubes (Figures released from Google) High-Yield Repairing Algorithms 63 T.-C. HUANG, NCUE

K-Map representing a Hypercube A 5 A 4 A 3 A 2 A 1 A 0 000 001 011 010 110 111 101 100 000 001 011 010 110 111 101 100 Implicant Cover Subcube High-Yield Repairing Algorithms 64 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Row 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 65 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Column 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 66 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Cluster 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 67 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Scattered Clusters probably due to address fluctuation 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 68 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Scattered Clusters probably due to address fluctuation 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 69 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Scattered Clusters probably due to address fluctuation 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 70 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Scattered Clusters probably due to address fluctuation 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 71 T.-C. HUANG, NCUE

More Multi-Fault Occurrence 000 000 001 010 011 100 101 110 111 Address Line Faults Scattered Clusters probably due to address fluctuation 001 010 011 100 101 110 111 High-Yield Repairing Algorithms 72 T.-C. HUANG, NCUE

Proposed VERA Verifier/Estimator for Redundancy Analysis Conditional-Probability-based Fault Distributor Uniformed-distribution p=1-y o First Faulty Address Condictional Probabilty of Driven Cells of a Driving Cell at (13, 10) (good) 0.22 0.215 p(row) p(col) 0.205 p(cluster) p(cube) p(random) 15 10 Poison Distribution 5 n trials 5 0 0 High-Yield Repairing Algorithms 73 T.-C. HUANG, NCUE 0.21 0.2 20 10 15 20

Number of Blocks (Trials) Result Histogram 2 x 104 1.8 1.6 1.4 1.2 1 0.8 #Good Blocks = 18,817 Original Yield = 18.8% #Faulty Blocks = 81,183 First-Fault Probability = 0.812 Probability of Following Fault Types: - Random: 0.100 - Row: 0.225 - Column: 0.225 - Cluster: 0.225 - Cubic: 0.225 0.6 0.4 0.2 0 0 20 40 60 80 100 Number of Faulty Cells per Memory Blocks High-Yield Repairing Algorithms 74 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 75 T.-C. HUANG, NCUE

Basic Concept Diameter (degree) n of an n-cube faulty cell k Qm n e.g., (011-0--1--) k-cube (Max.) distance from node to cube m+n-cube Q m+n Q k Hamming distance High-Yield Repairing Algorithms 76 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 77 T.-C. HUANG, NCUE

Row Adr. Dec. Hypercube-based Remapping n Col. Adr. Dec. Adr. m+n m+n m M-row N-column Memory Ternary CAM TCAM s Spare n-cube Memory 0 1 Dio m+n m+n Spare Col. Adr. Dec. Masked-Bit Concentrator Address Shifter Hit n High-Yield Repairing Algorithms 78 T.-C. HUANG, NCUE

from prior rows Proposed TCAM Design Mask-Bit-Readable TCAM Cell WL Mout0 Mout1 231 232 2311 2313 Qij A ij Aij 2314 BL BL WL of Spare Cube 2314 2313 2312 ML Mouti-1 Mouti Kij Kij KL BL BL KL MWL 233 RWmaski MATCHi Priority Encoder High-Yield Repairing Algorithms 79 T.-C. HUANG, NCUE

Address (Bubble) Shifter If matched by the TCAM comparison Extract the masked address bits to a sub-address Also called Masked Bit Concentrator Not necessarily in order but bijective (1-1) Base Address m+n Mask Bits m+n 1 0 1 1 0 1 0 1 Address Shifter 1 0 X 1 X X 0 X TCAM n Remapped Address High-Yield Repairing Algorithms 80 T.-C. HUANG, NCUE

Swapper in the Address Shifter Swapper in Binary Sorting Network ( A j, K j ) ( A j 1, K j 1) ' ' ( A j, K j ) ' ( A j, K ' 1 j 1 ) Only 1 Level of CMOS gates for 1 Stage A B if A>B, otherwise A B A if A>B, otherwise B High-Yield Repairing Algorithms 81 T.-C. HUANG, NCUE

In-order Remapped Address Address Shifter using a Parallel Sorter(2n) 241 (A 0, K 0 )=(?, 0) a a a a a (A' 0, K' 0 )=(a, 1) a (A 1, K 1 )=(a, 1)? c?? c (A' 1, K' 1 )=(b, 1) b (A 2, K 2 )=(?, 0)?? c b? (A' 2, K' 2 )=(c, 1) c (A 3, K 3 )=(b, 1) b???? (A' 3, K' 3 )=(d, 1) d (A 4, K 4 )=(?, 0) c?? c b (A' 4, K' 4 )=(0, 0) (A 5, K 5 )=(c, 1)?? b? d (A' 5, K' 5 )=(0, 0) (A 6, K 6 )=(?, 0)? b? d? (A' 6, K' 6 )=(0, 0) (A 7, K 7 )=(d, 1) d d d?? (A' 7, K' 7 )=(0, 0) Extracting the sub-address IN ORDER. High-Yield Repairing Algorithms 82 T.-C. HUANG, NCUE

Address Shifter using a Bitonic Sorter Parallel Sorter Half-Cleaner #inputs N n =log 2 N Parallel Sorter New Concentrator %Red. (Area) (Time) 4 2 3 2 33 8 3 6 4 33 16 4 10 7 30 32 5 15 11 27 Extracting the sub-address IN BIJECTION. High-Yield Repairing Algorithms 83 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 89 T.-C. HUANG, NCUE

Eg. Essential Spare Pivoting [3] Essential 000 001 010 011 100 101 110 111 0 4 1 3 000 001 010 011 Essential Valid 100 101 110 111 1 2 5 7 High-Yield Repairing Algorithms 90 T.-C. HUANG, NCUE

HYPERA (Redundancy Analysis) Modified Quine-McCluskey Algorithm Externally Repairing Repair-Rate Optimized Essential Cube Pivoting Algorithm Modified from Essential Spare Pivoting Algorithm for Hypercube-based Architecture Reduce the BIRA Complexity in a greedy manner. High-Yield Repairing Algorithms 91 T.-C. HUANG, NCUE

Modified QMA for External Analysis 1. Let the maximum degree of spare subcubes be n. Initialize all faulty cell addresses as subcubes of degree d 1 = 0. 2. Sort all subcubes of degree d 1 by weight. 3. Select any pair of subcubes q 1 of degree d 1 and q 2 of degree d 2 < d 1 if d 1 + d 2 ; merge them into a subcubes q of degree d if d 2 n = deg(sparecube). 4. Increment d 1 by 1. if d 1 n then go to step 2. 5. Execute the Essential Tabular Process (ETP) for all subcubes over all minterms. High-Yield Repairing Algorithms 92 T.-C. HUANG, NCUE

Modified QMA for External Analysis FCA 0 1 2 3... Imp1 V V Imp2 V V V V Imp3 V V Karnaugh Map : Don t Care Essential Table Espresso High-Yield Repairing Algorithms 93 T.-C. HUANG, NCUE

Row Address Example 1 of MQMA 0 1 2 3 4 5 Column Address 0 1 2 3 4 5 6 7 10 16 24 34 51 52 54 56 57 External Analysis Using an optimum algorithm Modified Quine-McKluskey Algorithm 0 0 1 3 2 6 7 5 4 6 7 Ternary Subcube Address 0---00 101--- --1-10 72 (Cell Address in Octal System) 10 24 34 51 52 54 56 57 16 72 0 1 2 3 4 5 6 7 High-Yield Repairing Algorithms 94 T.-C. HUANG, NCUE S 0 S 1 S 2 1 3 2 6 7 5 4 10 16 72 34 24 51 52 56 57 54

Heuristics of proposed ECPA within threshold degree existing repaired cells row or column subcube Essential maximum subcube cluster faulty cell detected within threshold radius r High-Yield Repairing Algorithms 95 T.-C. HUANG, NCUE

Proposed ECP Algorithm 1 initialize; 2 for each faulty cell address A{ 3 for each spare cube (C, V, E){ 4 if(v) 5 if(e) repaired by merging A to C; 6 else if A and C in a row/col/cluster(r) or d t<n 7 set Essential E and merge A to C; 8 else set Valid V and store C = A; 9 break; 10 } 11 if unrepaired for each non-essential cube C { 12 if(max_dist(a, C) n) set Essential and merge A to C;} 13 if unrepaired, failed and exit; 14 } 15 expand non-essential cubes with degree n; 16 set all Essential; 17 success; High-Yield Repairing Algorithms 96 T.-C. HUANG, NCUE

Example: Essential Cube Pivoting 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 Spare cube 0 Spare cube 1 Spare cube 2 Spare cube 3 111 001000 001--0 0-1--0 V E 010100 ---100 V E 101001 1010-- V E 111011 V E High-Yield Repairing Algorithms 97 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 98 T.-C. HUANG, NCUE

Number of Blocks (Trials) Case Study for Evaluation 2 x 104 1.8 1.6 1.4 1.2 1 0.8 #Good Blocks = 18,817 Original Yield = 18.8% #Faulty Blocks = 81,183 First-Fault Probability = 0.812 Probability of Following Fault Types: - Random: 0.100 - Row: 0.225 - Column: 0.225 - Cluster: 0.225 - Cubic: 0.225 0.6 0.4 0.2 0 0 20 40 60 80 100 Number of Faulty Cells per Memory Blocks High-Yield Repairing Algorithms 99 T.-C. HUANG, NCUE

Repair Rate (%) 100 90 80 Case Evaluation Repair Rate = 99.8% MQMA/External Repair Rate = 95% ECPA/BIRA Yr = 100% Yr = 96% 70 60 50 Proposed MQMA Proposed ECP MESP in [11] ESP in [3] 40 30 0 5 10 15 20 25 30 35 Spare Size (equivalent rows) Yo = 18.8% High-Yield Repairing Algorithms 100 T.-C. HUANG, NCUE

Layout (1/2) A 16K-Word Case (TVLSI2010SKLu, followed-up) High-Yield Repairing Algorithms 101 T.-C. HUANG, NCUE

Layout (2/2) MBIST: HOY s BRAINS RF: Artisan s Compiler CBD: Synopsys s DC P&R: Synopsys s SE Editor: Virtuoso/Cadence Status: Ready for small cases (128KB) Tutorial available Under verification Tape-in on Aug. High-Yield Repairing Algorithms 102 T.-C. HUANG, NCUE

Faulty Row Adr. Dec. Product Grading n Col. Adr. Dec. Adr. m+n m+n m M-row N-column Memory Ternary CAM TCAM s Spare n-cube Memory 0 1 Dio m+n m+n Spare Col. Adr. Dec. Masked-Bit Concentrator Address Shifter Hit n High-Yield Repairing Algorithms 103 T.-C. HUANG, NCUE

Outline Introduction Introduction to Memory Introduction to Magnetoresistive RAM Introduction to Memory Test Fault-Distributive Modeling Previous Work Effect-Cause Fault Analysis Proposed HYPERA Remapping Architecture Repairing Algorithms Redundancy Analysis Conclusions High-Yield Repairing Algorithms 104 T.-C. HUANG, NCUE

Conclusions A Hypercube-based Remapping Architecture and Efficient Algorithms are proposed. Repairing Rates can be highly improved up to almost 100%. Area overhead is small. Time penalty is still an issue. Effective yield can be still improved by sorting and disabling the access multiplexer for grade-a product. High-Yield Repairing Algorithms 105 T.-C. HUANG, NCUE

Our Sparrows Small as the sparrow is, it possesses all its internal organs. ( 麻雀雖小, 五臟俱全 ) -- Chinese sayings High-Yield Repairing Algorithms 106 T.-C. HUANG, NCUE

References 1. A. Allan et. al. Test and test equipment, in 2009 technology roadmap for semiconductors, p.29, TST-6, 2009. 2. Y. Zorian and S. Shoukourian, Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield, IEEE Design & Test of Computers, vol. 20, no. 3, May-June 2003, pp. 58-66. 3. C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, Built-In Redundancy Analysis for Memory Yield Improvement, IEEE Trans. on Reliability, vol. 52, no. 4, Dec. 2003, pp. 386 399. 4. L.-T. Wang, C.-W. Wu and X. Wen. "VLSI Test Principles and Architectures." ISBN 10:0-12-370597-5, NY, Elsevier, 2006. 5. P. Mazumder and Y. S. Jih, A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits, IEEE Trans. CAD IC Circuits Syst., vol. 12, no. 1, pp. 24 36, Jan. 1993. 6. T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, A built-in self-repair analyzer (CRESTA) for embedded DRAMs, in Proc. of IEEE International Test Conference, pp. 567-574, October 2000. 7. W. Jeong, T. Han and S. Kang. An Advanced BIRA using parallel sub-analyzers for embedded memories. In Proc. IEEE International SoC Design Conference, pp.249-252, 2009. 8. S. Hamdioui and A. J. van de Goor, Efficient Tests for Realistic Faults in Dual-Port SRAMs, IEEE Trans. on Computers, vol. 51, no. 5, May 2002, pp. 460-473. 9. Y. N. Shen, N. Park, and F. Lombardi, Spare Cutting Approaches for Repairing Memories, Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, Austin, Texas, USA, pp.106-111, October 1996. 10. M. Lee and C.-W. Wu, Method for Repairing Memory and System thereof. ROC Patent No.200921690, disclosed on May 16, 2009. 11. S.-K. Lu, C.-L. Yang, Y.-C. Hsiao and C.-W. Wu. Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Trans. on VLSI, vol. 18, no.2, pp.184-193, 2010. 12. R. Nair, S.M. Thatte and J.A. Abraham, "Efficient Algorithms for Testing Semiconductor Random- Access Memories", IEEE Transactions on Computers, Vol. C-27, No. 6, June 1978, pp. 572-576. 13. P. Ohler, S. Hellebrand, and H.-J. Wunderlich, An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy, in Proc. of the 12th IEEE European Test Symposium, pp. 91-96, May 2007. 14. T.-C. Huang, An Address Remapping Architecture and Memory Repairing Method thereof, ROC Patent 99141225, Nov. 30, 2010. 15. M. Malek, A. Mourad and M. Pandya, Topological Testing, in Proc. International Test Conference, pp.103-110, 1989. 16. J. Bruck and C.-T. Ho, Fault-Tolerant Cube Graphs and Coding Theory, IEEE Trans. Information Theory, vol.42, no.6, pp.2217-2221, 1996. 17. K.E. Batcher, Sorting networks and their applications, in Proc. the AFIPS Spring Joint Computer Conference, vol.32, pp.307-314, 1968. 18. M. S. Paterson, Improved sorting networks with O(log N) depth, Algorithmica vol.5, no. 1, pp. 75 92, 1990. 19. E. J. McCluskey, Minimzatlon of Boolean functions, J. Bell Syst. Tech., vol.35, no.5, pp.1417-1444, 1956. 20. L. Kraus and I. P. Batinic. Built-in spare row and column replacement analysis system for embedded memories, US Patent No. 6,304,989, Oct. 16, 2001. High-Yield Repairing Algorithms 107 T.-C. HUANG, NCUE

Thank you for your attention! High-Yield Repairing Algorithms 108 T.-C. HUANG, NCUE