Advanced Reliable Systems (ARES) Laboratory. National Central University Jhongli, Taiwan

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1 Chapter 7 Memory Testing Jin-Fu Li Advanced Reliable Systems (ARES) Laboratory Department of Electrical Engineering National Central University Jhongli, Taiwan

2 Outline Importance of Embedded Memories RAM Functional Faults March Tests Converting Bit-Oriented Oi td RAM Tests into Word- Oriented RAM Tests RAM BIST Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

3 Embedded Memory The Key to SOC Embedded memory is becoming more central to integrated circuit design Historically, ICs were dominated by the logic functions, with memory being external Today, an SOC contains many memory blocks of different sizes, shapes and functionality Typically, embedded memories represent about 30%~50% SOC area The Semiconductor Industry Association (SIA) predicts that 90% of the SOC s surface will be memory by 2011 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

4 Embedded Memory The Key to SOC SOC memory continues to increase Memory Area Reused Logic Area New Logic Area 20% 16% 52% 71% 83% 90% 94% 64% 16% 13% 32% 9% 6% 16% 4% 8% 4% 2% * 11* 14* *Foreast Source: SIA, ITRS, 2000 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

5 Embedded Memory Quality During manufacture Yield Exponential yield model AD Y = e, where A and D denote the area and defect density, respectively After manufacture Reliability During use Soft error rate Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

6 Quality During Manufacture Issues of embedded memory As the density of transistors is increased, the D is increased compared to logic About 2X logic for high density 6-T SRAM Solutions Redundancy & laser repair using ATE Error correction code (ECC) Redundancy & repair Achieve yield parity with logic, or better About 3% area overhead Recommended over 1Mb Laser repair manufacturing flow Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

7 ECC Quality During Manufacture Detect/repair defects in individual words 25-30% area overhead Ex: 6 extra bits for single bit correction in 32 bit words Latency penalty At least one clock cycle latency penalty Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

8 Quality-Insurance Methods for Memories in SOCs Memory Tester Laser Repair Memory Tester.Large Capture Memory.Redundancy analysis.swap the defective cells.test the repaired memories Conventional test and repair approaches 1. Long testing time 2. Expensive memory tester and logic tester are needed Logic Tester.Test the remaining non-memory components.test Built-In Self-Test (BIST) BIST & BISR approaches 1. Short testing time 2. Only cheap logic tester is needed.diagnostics.redundancy allocation.swap the defective cells Built-In Self-Diagnosis (BISD) Built-In Redundancy d Analyzer (BIRA) Redundancy Reconfiguration Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

9 2-D Memory Architecture S 0 Word A 0 A 1 A k-1... Row De ecoder S 1 Word i S n A 0 A j-1 Column Decoder Word ni-1 Sense Amplifier Read/Write Circuit 2 m -bit Input/Output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

10 3-D Memory Architecture ock Blo olumn Co Row Input/Output Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10

11 Memory Testing Fault modeling Test generation Fault simulation DFT & DFM Wafer fabrication Repair Die separation, packaging Burn-in Shipment Probe test Post-repair Probe test Pre-BI Test Final Test Test-Preparation Phase Test-Execution Phase Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11

12 Functional RAM Model address address latch column decoder row deco oder memory cell array write driver sense amplifier read/write & enable data register data in data out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12

13 Reduced Functional Model data Rea ad/write logic Mem mory cell array ad ddress de ecoder ad dress The address latch, the row, and the columndecoder are combined to the address decoder They y all concern addressing the right cell or word The write driver, the sense amplifier, and the data register are combined to the read/write logic They all concern the transport of data from and to the memory cell array Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13

14 Reduced Functional Faults Stuck-at k fault (SAF) Definition: The logic value of a stuck-at (SA) cell or line is always 0 or 1. It is always in state 0 or in state 1 and cannot be changed to the opposite state Detection requirement: From each cell or line, a 0 or 1 must be read Transition fault (TF) Definition: fiii A cell that fails to undergo a 0 to 1 transition when it is written is said to contain an up transition fault A down transition fault indicates that a cell fails to undergo a 1 to 0 transition Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14

15 Reduced Functional Faults A TF can be thought of as a set/reset (S/R)-type flipflop with a SAF on the set or reset input SA0 S Q R Q Detection requirement: Each cell should undergo up and down transitions and be read after each transition before undergoing further transitions Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15

16 State Diagram for SAFs & TFs w1 w0 S 0 S 1 w1 w0 State diagram of a good cell w1 w0 S 0 w1 w0 S 1 w1 w0 S 0 S w0 1 SA0 fault SA1 fault TFu w1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16

17 Reduced Functional Faults Coupling faults (CFs) 2-cell coupling faults Different types of CFs CFin Inversion CF (CFin) Idempotent CF (CFid) State CF (CFst) Dynamic CF (CFd) A 0 to 1 (or 1 to 0) transition in one cell inverts the content of a second cell An CFin can be thought of as a D-type flip-flop flop with an extra clock input C d and the Q output tied to the D input, as depicted in the following figure. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 17

18 Reduced Functional Faults D Q CFid C n C d Q A 0 to 1 (or 1 to 0) transition in one cell forces the content of a second cell to a certain value, 0 or 1. An idempotent coupling fault can be thought of as an S/R-type flip-flop flop with an OR-gate in the Set or Reset line, as depicted in the following figure. S n is the normal set input whereas S d is the undesired set input due to coupling with one or more other flip flops. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18

19 Reduced Functional Faults S n S d S Q CFst R n R Q A 0 or 1 state in one cell forces the content of a second cell to a certain value, 0 or 1 It can be thought of as a D-type flip-flop with an OR/AND-gate in the data line (D), as depicted in the following figure. D n is the normal set input whereas D d is the undesired set input due to coupling with one or more other flip flops Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 19

20 Reduced Functional Faults D n D d D Q clk Q Dynamic Coupling Fault (CF d ) Occur between cells in different words. A read or write operation on one cell forces the content of the second cell either 0 or 1. Denoted as <rx wy; z> where denotes the or of the read and write operations Four possible CF d faults <r0 w0;0>, <r0 w0;1>,<r1 w1;0>, and <r1 w1;1> Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 20

21 State Diagrams for CFin & CFid w0/i, w0/j S 00 w1/j w0/j S 01 w0/i, w1/j w0/i w1/i w0/i w1/i w1/j w1/i, S 10 S w1/i, 11 w0/j w0/j w1/j State diagram of two good cells w0/i, w0/j w1/i, w0/j S 00 w0/j w1/j S 01 w0/i w1/i w0/i w1/i w1/j S 10 w0/j S 11 State diagram of an CFin<u;i> w0/i, w1/j w1/i, w1/j w0/i, w0/j w0/i, S 00 S w0/j 01 w1/j w1/j w0/i w1/i w0/i w1/i w1/i, w0/j w1/j S 10 S w1/i, 11 w0/j w1/j State diagram of an CFid<u;1> Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 21

22 Summary of CFs Note that t all definitions iti talk about single-way faults, that is, the presence of a CF from cell i to cell j does not imply the presence of a CF from cell j to cell i. Suppose that a transition or state in cell j can induce a coupling fault in cell i. Cell i is then said to be coupled cell (or victim); cell j is called the coupling cell (or aggressor). A test that has to detect and locate all coupling faults should satisfy For all coupled cells, each cell should be read after a series of possible coupling faults may have occurred Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 22

23 BL Relation Between Faults & Defects Df Defect d(i 1 (inverse node shorted to V dd ) causes a SA0 fault Defect d 2 (true node shorted to V ss ) causes a SA0 fault V dd Defect d 3 (open true node gate) cause a SA1 fault R R d 7 Df d( d 1 d4 WL causes all cells after the WL fault to be inaccessible (AF) d 5 d 3 d 2 d 6 Defect d 5 (a short between the true node and BL) will pull BL down if V the cell contains a 0, but will not ss affect BL if the cell contains 1. This is the state coupling fault <0;0> BL Defect d 6 (short between inverse node and BL ) is similar, as is the state coupling fault <1;1> Defect d 7 (open BL ) prevents cells after the open defect from passing a logic 1 value on BL Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 23

24 Relation Between Faults & Defects Defect d 1 (a word line connected to V ss ) causes all cells in the word line to be stuck open. V dd A defect in the poly silicon layer covering a diffusion region may result R R in the creation of an extra pass transistor. This defect (d 2 ) causes a d transition fault. 3 WL Defect d 3 (a broken pull up resistor) introduces a data retention fault. If the d 1 cell is not accessed, the cell node with d V the broken pull up resistor can be 2 ss floating high or active low. If the node is floating high, the leakage current BL BL from the cell node to the substrate will decline the voltage at the node. If the node voltage passes the threshold voltage V th the data in the cell will invert. If the node is active low, the cell will function correctly. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 24

25 March Tests A march test consists of a finite sequence of march elements A march element A finite sequence of Read and/or Write operations applied to every cell in memory in either increasing address order (cell 0 to cell n-1) or decreasing address order (cell n-1 to cell 0) All operations of a march element are done before proceeding to the next address The march tests are a preferred method for RAM testing Linear complexity, regularity, and symmetry Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 25

26 March Test Notation rx: a read x operation wx: a write x operation : increasing addressing sequence (from 0 to n- 1) : decreasing addressing sequence (from n-1 to 0) : either increasing or decreasing addressing sequence Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 26

27 An Example of March Test An example of march test { ( w1); ( r1, w0)} (w1) Addressing Addressing Addressing Addressing cell 0 cell 1 cell 2 cell 3 1 X X X X X 1 X 1 1 Initial state X X X X Addressing cell 0 Addressing cell 1 Addressing cell 2 Addressing cell (r1,w0) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 27

28 March Tests for SAFs & TFs MATS+: { ( w0); ( r0, w1); ( r1, w0)} MATS+ detection of SA0 fault Good memory Good memory Good memory after M0 after M1 after M2 Bad memory after M Bad memory after M1 Bad memory after M2 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 28

29 March Tests for SAFs & TFs MATS+ detection of SA1 fault Good memory after M Good memory after M1 Good memory after M Bad memory after M Bad memory after M Bad memory after M2 MATS+ detection of TFu & TFd can be proved in the same way Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 29

30 Tests for Detecting SAFs & TFs Conditions for detecting SAFs & TFs SAFs & TFs can be detected by a march test which contains the following two march elements (or single march element containing both elements) (..., w0, r0,...) (..., w 1, r1,...) to detect SA1 faults and TFd to detect SA0 faults and TFu Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 30

31 March C -: Detection of CFs March Tests for CFs { ( w0); ( r0, w1); ( r1, w0); ( r0, w1); ( r1, w0); ( r0)} M1 is executed Cell 0 is Cell 1 is Cell 2 is Cell 3 is Cell 8 is addressed addressed addressed addressed addressed M3 is executed Cell 0 is addressed Cell 1 is addressed Cell 2 is addressed Cell 3 is addressed Cell 8 is addressed Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 31

32 March Tests for CFs Conditions for detecting ti CFs A march test which contains one of the two pairs of march elements of Case A & Case B can detect simple CFs (CFin, CFst, CFid) Case A ( rx,, wx ) ( rx,, wx ) Case B ( rx,, wx) ( rx,, wx) 1. ( rx,, wx) ( rx,, wx) 2. ( rx,, wx ) ( rx,, wx ) A.1 (A.2) will sensitize the CFs, and it will detect the fault, when the value of the fault effect is x (x), by the rx (rx ) operation of the first (second) march element when the coupled cell has a higher (lower) address than the coupling cell Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 32

33 March Tests for DRFs Data retention faults (DRFs) DRF has two subtypes A stored 1 will become a 0 after a time T A stored 0 will become a 1 after a time T Conditions for detecting DRFs Any march test can be extended to detect DRFs The detection of each of the two DRF subtypes requires that a memory cell be written into the corresponding logic states t If we are interested in detecting simple DRFs only The delay elements can be placed between any two pairs of march elements, e.g., ( rx,, wx) ; Del; ( rx,, wx ) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 33

34 Tests for Word-Oriented Memories Fault models for word-oriented memories (WOMs) Only the class of memory cell array faults for bitoriented memories (BOMs) has to be extended in order to cover WOMs The fault models for WOMs can be classified into two classes Single-cell faults SAFs, TFs, data retention faults (DRFs), etc. Faults between memory cells CFs Two classes of faults between memory cells for WOMs needed d to be considered d Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 34

35 Tests for Word-Oriented Memories CFs in BOMs CFs in WOMs Inter-word CFs & intra-word CFs Intra-word CF Inter-word CF Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 35

36 Converting March Tests Any given BOM march test can be converted to a WOM march test With additional tests to cover intra-word faults A WOM march test is a concatenation of two march tests {Inter-word march test, intra-word march test} The inter-word march test can directly be obtained from the BOM march test t Replace the bit-operation r0, w0, r1, and w1 with the word-operation operation rd, wd, rd, and wd, where D is called data background Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 36

37 Converting March Tests The intra-word faults can be detected by a single march element with different operations and data backgrounds E.g., g intra CFst can be covered by ( wd, rd,..., wd, rd 1 1 n n) with various data backgrounds (DBs) Note that the DBs can be applied in any order The above intra-word test can be modified as follows, without any impact on the fault coverage Extra Read operations can be added The e single march element e e can be divided ded into any number of march elements, and for each march element the addressing order can be chosen freely Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 37

38 Compact WOM Tests If you have a bit-oriented march test, then you can obtain a compact WOM test with Replace the bit-operation r0, w0, r1, and w1 with all-0 and all-1 data backgrounds Concatenate a march element ( wd, wd, rd, wd, rd ) for d={ , , } For example, the March C- can be extended das follows to test a memory with 4-bit words { ( w0000 ); ( r0000, w1111); ( r0000, w11111); ( r1111, w0000 ); ( w0101, w1010, r1010, w0101, r0101); ( w 0011, w 1100, r 1100, w 0011, r 0011)} ( r11111, w0000 ); ( r0000 ); Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 38

39 Memory Organization & WOM Tests WOMs can be organized internally in many different ways Adjacent; interleaved; sub-arrays adjacent interleaved sub-array For sub-array organized WOMs, the BOM tests for CFs will detect the CFs within a B-bit word such that no intra-word tests are required Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 39

40 RAM BIST A typical RAM BIST consists of the following components Controller, test pattern generator, and comparator Controller Generate control signals to the test pattern generator & the memory under test Test pattern generator (TPG) Generate the required test patterns and Read/Write signals Comparator Evaluate the response Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 40

41 Typical RAM BIST Architecture Normal I/Os Test Controller Test Pattern Generator Test Collar RAM Go/No-Go Comparator Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 41

42 RAM BIST In general, two BIST approaches have been proposed p for the RAMs FSM-based RAM BIST ROM-based RAM BIST Controller Generate control signals to the test pattern generator & the memory under test Test pattern generator (TPG) Generate the required test patterns and Read/Write signals Comparator Evaluate the response Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 42

43 Controller An example of the state diagram of controller W0 S 0 NOT last address? R0 W1 S 1 S 2 NOT last address? R1 W0 S 3 S 4 NOT first address? R0 W1 S 5 S 6 NOT first address? End S 7 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 43

44 Programmable RAM BIST An example of the programmable RAM BIST Normal I/Os BSI BSC BRS Co ontroller r CMD TGO ENA TPG & Compa Test Collar RAM BGO DONE rator CLK BNS Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 44

45 FSM State Diagram of the Controller Idle BRS=1 DONE=1 BSC=1 Shift_cmd BSC=0 Get_cmd Apply ENA=1 DONE=0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 45

46 Programmability The programmability can be achieved by using test command The test command format U/D OP Data background U/D: ascending/descending address sequence OP: test operations For example, wa, rawa, rawa ra, warawa ra, etc. Data backgrounds The width of each field affects the programmability of the BIST design For example, if 4 bits are used for OP, then only 16 possible test operations can be generated Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 46

47 FSM State Diagram of the TPG Idle ENA=0 ENA=1 Init Null=1 Null=0 DONE/GO Ifetch Exec No-Go Dfetch Error=1 Compare Error=0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 47

48 A typical ROM model ROM-Based BIST X m p ROM m+ p 2 ( n + p) n p n Register Y Source: R. Senhadji-Navarro, et al., Electronic Letters, 2004 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 48

49 ROM-Based BIST A typical ROM model for March test elements March Address element CEN WEN Invert Addr_Incr State 000_ Idle 001_ wa 010_ ra 011_ ra 011_ wa 100_ ra 100_ wa Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 49

50 Serial BIST Today s telecommunication ICs often have a variety of multi-port memories on one chip Typical RAM BISTs evaluate all the bits of a memory word in parallel as it is read We can encounter significant problems when applying these BIST schemes to chips that have multiple embedded RAMs of varying sizes and port configurations The area cost of these BIST designs would be unacceptably high One better solution is a serial BIST technique To share BIST design among several RAMs Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 50

51 Benefits of Serial BIST Only a small amount of additional circuitry is required Only a few lines are needed to connect the RAM to the test controller Several RAM blocks easily share the BIST controller hardware The serial-access mode does not compromise the RAM cycle time Existing memory designs do not need any modification to use the serial interface Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 51

52 Serial-Data-Path Connection Row decoder C i C i+1 Column decoder Write Read BIST on From previous output or serial input Latch Latch To next test input or serial input O i O i+1 I i I i+1 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 52

53 Serial Shift Operation An example of serial shift operations for the match element (R0W1) Time Operation Serial Word Serial in content out 0 X 0 X 1 R0 X W R W X 1 X 0 5 R0 1 6 W R W Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 53

54 Serial March (SMarch) Assume that a RAM has W words, and each word contains C bits A Read operation is denoted by R0, R1, or Rx, depending on the expected value at the serial output (x=don t care) For a write operation, the terms W0 or W1 are used and only the serial input is forced to the value indicated The SMarch modified from March C- is as follows C C C ( RW RxW 0) ( R 0, W 0) ; ( R 0, W 1) ( R 1, W 1) ( R1, W 0) C ( R 0, W 0) ( C ; ( R 0, W 1) C C C R 1, W 0) ( R 0, W 0) ; ( R 0, W 0) ( R 0, W 0) C C ( R1, W 1) C C Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 54

55 Serial BIST Architecture BIST GO Done Counters Controller SO SI Control Data out lsb msb Data in Address C-1 Timing generator Multiplexer er Multiplexer er C C Multiplexer er Address Data in Data out Control RAM (W words of C bits) Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 55

56 References [1] M. Sachdev, Defect Oriented Testing for CMOS Analog and Digital Circuits, Kluwer Academic, [2] M.-L. Bushnell and V.-D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Kluwer Academic, [3] A. J. van de Goor and C. A. Verruijt, An Overview of Deterministic i i Functional RAM Chip Testing, ACM Computing Surveys, vol. 22, no. 1, March [4] A. J. van de Goor, I. B. S. Tlili, and S. Hamdioui, Converting March Tests for Bit-Oriented Memories into Tests for Bit-Oriented Memories, MTDT, pp , [5] A. J. van de Goor and G. N. Gaydadjiev, March U: a test for unlinked memory faults, IEE Proc. Circuit it Devices Syse., vol.144, no. 3, pp , [6] D. S. Suk and S. M. Reddy, A march test for functional faults in semiconductor random-access access memories IEEE Trans. Comput., C-30, 12, pp , [7] K. L. Cheng, M. F. Tsai, and C. W. Wu, Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories, IEEE Trans. CAD, vol.21, no.11, pp , 1336 nov., [8]C. F. Wu, C. T. Huang, and C. W. Wu RAMSES: a fast memory fault simulator, DFT99, pp , [9] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal, Serial interfacing for embedded-memory testing, IEEE D&T, pp.52-63, apr Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 56

57 References [10] C. W. Wu, VLSI testing & design for testability II: Memory built-in self-test, [11] A. J. van de Goor and C. A. Verruijt, An Overview of Deterministic Functional RAM Chip Testing, ACM Computing Surveys, vol. 22, no. 1, March [12] A. K. Sharma, Semiconductor Memories Technology, Testing, and Reliability, IEEE PRESS, [13] R. Dekker, F. Beenker, and L. Thijssen, Fault Modeling and Test Algorithm Development for Static Random Access Memories, Int. Test Conf., pp , [14] M. Sachdev, Defect Oriented Testing for CMOS Analog and Digital it Circuits, Kluwer Academic, [15] B. F. Cockburn, Tutorial on Semiconductor Memory Testing, JETTA, pp , 336, Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 57