COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. Radhakrishnan Professor of Computer Science and Software Engineering Concordia University Montreal, Canada Delhi-110092 2011
COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman and T. Radhakrishnan 2007 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN-978-81-203-3200-3 The export rights of this book are vested solely with the publisher. Fourth Printing July, 2011 Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111, Patparganj Industrial Estate, Delhi-110092 and Printed by Rajkamal Electric Press, Plot No. 2, Phase IV, HSIDC, Kundli-131028, Sonepat, Haryana.
CONTENTS Preface xi 1. Computer Systems A Perspective 1 13 Learning Objectives 1 1.1 Introduction 1 1.2 A Programmer s View of a Computer System 3 1.3 Hardware Designer s View of a Computer System 5 1.4 Objectives of the Computer Architect 7 1.5 Some Invariant Principles in Computer design 9 Summary 11 Exercises 12 2. Data Representation 14 38 Learning Objectives 14 2.1 Introduction 14 2.2 Numbering Systems 17 2.3 Decimal to Binary Conversion 19 2.4 Binary Coded Decimal Numbers 23 2.4.1 Weighted Codes 25 2.4.2 Self-Complementing Codes 25 2.4.3 Cyclic Codes 26 2.4.4 Error Detecting Codes 28 2.4.5 Error Correcting Codes 29 2.5 Hamming Code for Error Correction 30 2.6 Alphanumeric Codes 32 2.6.1 ASCII Code 33 2.6.2 Indian Script Code for Information Interchange (ISCII) 34 Summary 35 Exercises 37 iii
iv 3. Basics of Digital Systems 39 97 Learning Objectives 39 3.1 Boolean Algebra 40 3.1.1 Postulates of Boolean Algebra 40 3.1.2 Basic Theorems of Boolean Algebra 41 3.1.3 Duality Principle 42 3.1.4 Theorems 42 3.2 Boolean Functions and Truth Tables 43 3.2.1 Canonical Forms for Boolean Functions 44 3.3 Binary Operators and Logic Gates 46 3.4 Simplifying Boolean Expressions 48 3.5 Veitch Karnaugh Map Method 50 3.5.1 Four-Variable Karnaugh Map 54 3.6 NAND and NOR Gates 60 3.7 Design of Combinatorial Circuits with Multiplexers 64 3.8 Programmable Logic Devices 70 3.8.1 Realization with FPLAs 70 3.8.2 Realization with PALs 72 3.9 Sequential Switching Circuits 74 3.10 A Basic Sequential Circuit 74 3.11 Flip-Flops 77 3.12 Counters 85 3.12.1 A Binary Counter 85 3.12.2 Synchronous Binary Counter 86 3.13 Shift Registers 88 Summary 92 Exercises 96 4. Arithmetic and Logic Unit I 98 147 Learning Objectives 98 4.1 Introduction 98 4.2 Binary Addition 99 4.3 Binary Subtraction 101 4.4 Complement Representation of Numbers 103 4.5 Addition/Subtraction of Numbers in 1 s Complement Notation 104 4.6 Addition/Subtraction of Numbers in Two s Complement Notation 107 4.7 Binary Multiplication 109 4.8 Multiplication of Signed Numbers 112 4.9 Binary Division 113 4.10 Integer Representation 116 4.11 Floating Point Representation of Numbers 117 4.11.1 Binary Floating Point Numbers 120 4.11.2 IEEE Standard Floating Point Representation 123
v 4.12 Floating Point Addition/Subtraction 127 4.12.1 Floating Point Multiplication 129 4.12.2 Floating Point Division 130 4.13 Floating Point Arithmetic Operations 130 4.14 Logic Circuits for Addition/Subtraction 132 4.14.1 Half and Full-Adder Using Gates 133 4.14.2 A Four-bit Adder 135 4.14.3 MSI Arithmetic Logic Unit 139 4.15 A Combinatorial Circuit for Multiplication 142 Summary 143 Exercises 145 5. Arithmetic Logic Unit II 148 170 Learning Objectives 148 5.1 Introduction 148 5.2 Algorithmic State Machine 149 5.3 Algorithmic Representation of ASM Charts 157 5.4 Designing Digital Systems Using ASM Chart 159 5.5 Floating Point Adder 165 Summary 168 Exercises 169 6. Basic Computer Organization 171 204 Learning Objectives 171 6.1 Introduction 171 6.2 Memory Organization of SMAC+ 172 6.3 Instruction and Data Representation of SMAC+ 173 6.4 Input/Output for SMAC+ 177 6.5 Instruction Set of SMAC+ 177 6.5.1 Instruction Set S1 of SMAC+ 178 6.5.2 Instruction Formats of SMAC+ 178 6.6 Assembling the Program into Machine Language Format 180 6.7 Simulation of SMAC+ 181 6.8 Program Execution and Tracing 183 6.9 Expanding the Instruction Set 185 6.10 Vector Operations and Indexing 188 6.11 Stacks 190 6.12 Modular Organization and Developing Large Programs 193 6.13 Enhanced Architecture SMAC++ 197 6.13.1 Modifications in the Instruction Formats for SMAC++ 199 6.14 SMAC++ in a Nutshell 200 Summary 201 Exercises 202
vi 7. Central Processing Unit 205 240 Learning Objectives 205 7.1 Introduction 205 7.2 Operation Code Encoding and Decoding 207 7.3 Instruction Set and Instruction Formats 210 7.3.1 Instruction Set 211 7.3.2 Instruction Format 212 7.4 Addressing Modes 216 7.4.1 Base Addressing 217 7.4.2 Segment Addressing 218 7.4.3 PC Relative Addressing 219 7.4.4 Indirect Addressing 219 7.4.5 How to Encode Various Addressing Modes 220 7.5 Register Sets 221 7.6 Clocks and Timing 223 7.7 CPU Buses 226 7.8 Dataflow, Data Paths and Microprogramming 229 7.9 Control Flow 233 7.10 Summary of CPU Organization 236 Summary 238 Exercises 239 8. Assembly Language Level View of Computer System 241 272 Learning Objectives 241 8.1 Introduction 241 8.2 Registers and Memory 242 8.3 Instructions and Data 244 8.4 Creating a Small Program 246 8.5 Allocating Memory for Data Storage 248 8.6 Using the Debugger to Examine the of Registers and Memory 250 8.7 Hardware Features to Manipulate Arrays of Data 252 8.8 Stacks and Subroutines 256 8.9 Arithmetic Instructions 260 8.10 Bit Oriented Instructions 261 8.11 Input and Output 263 8.12 Macros in Assembly Language 265 8.13 Instruction Set View of Computer Organization 268 8.14 Architecture and Instruction Set 269 Summary 271 Exercises 271
vii 9. Memory Organization 273 296 Learning Objectives 273 9.1 Introduction 273 9.2 Memory Parameters 274 9.3 Semiconductor Memory Cell 276 9.3.1 Dynamic Memory Cell 277 9.3.2 Static Memory Cell 277 9.3.3 Writing Data in Memory Cell 278 9.3.4 Reading the of Cell 279 9.4 IC Chips for Organization of RAMs 280 9.5 2D Organization of Semiconductor Memory 282 9.6 2.5D Organization of Memory Systems 284 9.7 Dynamic Random Access Memory 286 9.8 Error Detection and Correction in Memories 289 9.9 Read Only Memory 290 9.10 Dual-Ported RAM 293 Summary 294 Exercises 295 10. Cache and Virtual Memory 297 331 Learning Objectives 297 10.1 Introduction 297 10.2 Enhancing Speed and Capacity of Memories 298 10.3 Program Behaviour and Locality Principle 299 10.4 A Two-Level Hierarchy of Memories 301 10.5 Cache Memory Organization 304 10.6 Design and Performance of Cache Memory System 315 10.7 Virtual Memory Another Level in Hierarchy 318 10.7.1 Address Translation 319 10.7.2 How to Make Address Translation Faster 321 10.7.3 Page Table Size 322 10.8 Page Replacement Policies 323 10.8.1 Page Fetching 326 10.8.2 Page Size 326 10.9 Combined Operation of Cache and Virtual Memory 327 Summary 328 Exercises 330 11. Input-Output Organization 332 380 Learning Objectives 332 11.1 Introduction 333 11.2 Device Interfacing 334 11.3 Overview of I/O Methods 336
viii 11.4 Program Controlled Data Transfer 338 11.5 Interrupt Structures 340 11.5.1 Single Level Interrupt Processing 341 11.5.2 Handling Multiple Interrupts 343 11.6 Interrupt Controlled Data Transfer 344 11.6.1 Software Polling 344 11.6.2 Bus Arbitration 345 11.6.3 Daisy Chaining 346 11.6.4 Vectored Interrupts 347 11.6.5 Multiple Interrupt Lines 348 11.6.6 VLSI Chip Interrupt Controller 349 11.6.7 Programmable Peripheral Interface Unit 350 11.7 DMA Based Data Transfer 351 11.8 Input-Output (I/O) Processors 356 11.9 Bus Structure 357 11.9.1 Structure of a Bus 357 11.9.2 Types of Bus 358 11.9.3 Bus Transaction Type 358 11.9.4 Timings of Bus Transactions 358 11.9.5 Bus Arbitration 361 11.10 Some Standard Buses 363 11.11 Serial Data Communication 365 11.11.1 Asynchronous Serial Data Communication 366 11.11.2 Asynchronous Communication Interface Adapter (ACIA) 366 11.11.3 Digital Modems 367 11.12 Local Area Networks 369 11.12.1 Ethernet Local Area Network Bus Topology 369 11.12.2 Ethernet Using Star Topology 373 11.12.3 Wireless LAN 374 11.12.4 Client-Server Computing Using LAN 375 Summary 376 Exercises 378 12. Advanced Processor Architectures 381 429 Learning Objectives 381 12.1 Introduction 381 12.2 General Principles Governing the Design of Processor Architecture 382 12.2.1 Main Determinants in Designing Processor Architecture 382 12.2.2 General Principles 385 12.2.3 Modern Methodology of Design 386 12.2.4 Overall Performance of a Computer System 390 12.3 History of Evolution of CPUs 391 12.4 RISC Processors 395
ix 12.5 Pipelining 397 12.6 Instruction Pipelining in RISC 400 12.7 Delay in Pipeline Execution 403 12.7.1 Delay due to Resource Constraints 403 12.7.2 Delay due to Data Dependency 405 12.7.3 Pipeline Delay due to Branch Instructions 407 12.7.4 Hardware Modification to reduce Delay due to Branches 408 12.7.5 Software Method to reduce Delay due to Branches 412 12.7.6 Difficulties in Pipelining 414 12.8 Superscalar Processors 416 12.9 Very Long Instruction Word (VLIW) Processor 418 12.10 Some Example Commercial Processors 419 12.10.1 Power PC 620 420 12.10.2 Pentium Processor 421 12.10.3 IA-64 Processor Architecture 423 Summary 425 Exercises 426 13. Parallel Computers 430 473 Learning Objectives 430 13.1 Introduction 431 13.2 Classification of Parallel Computers 432 13.2.1 Flynn s Classification 432 13.2.2 Coupling between Processing Elements 435 13.2.3 Classification Based on Mode of Accessing Memory 435 13.2.4 Classification Based on Grain Size 436 13.3 Vector Computers 439 13.4 Array Processors 441 13.5 Shared Memory Parallel Computers 442 13.5.1 Synchronization of Processes in Shared Memory Computers 442 13.5.2 Shared Bus Architecture 446 13.5.3 Cache Coherence in Shared Bus Multiprocessor 447 13.5.4 State Transition Diagram for MESI Protocol 449 13.5.5 A Commercial Shared Bus Parallel Computer 453 13.5.6 Shared Memory Parallel Computer Using an Interconnection Network 454 13.6 Distributed Shared Memory Parallel Computers 455 13.7 Message Passing Parallel Computers 461 13.8 Cluster of Workstations 465 13.9 Comparison of Parallel Computers 466 Summary 468 Exercises 470
Computer Organization And Architecture Publisher : PHI Learning ISBN : 9788120332003 Author : V Rajaraman And T Radhakrishnan Type the URL : http://www.kopykitab.com/product/6182 Get this ebook