Quartus Counter Example Last updated 9/6/18
Create a logic design from start to a DE10 implementation This example uses best design practices This example is not about creating HDL The HDL code will be provided without explanation 2 tj
Flow MyDesign_tb.vhdl MyDesign.vhdl MyDesign_de10.vhdl 3 tj
Flow Create project Create HDL code Verify RTL visually Create testbench Verify operation Create DE10 implementation HDL Compile Verify RTL visually Program DE10 board Verify operation manually 4 tj
Flow MyDesign_tb.vhdl MyDesign.vhdl MyDesign_de10.vhdl 5 tj
Create a counter Binary wrapping count N bits Up/down Test the design using ModelSim Implement an 8 bit version on the DE10 Reset and direction switches Count value LEDs Clock divider 3Hz operation 6 tj
Flow MyDesign_tb.vhdl MyDesign.vhdl MyDesign_de10.vhdl 7 tj
Create a new Project Use the Quartus Project Setup notes as a guide Switch to Files view mode Note: the correctly named SDC file is visible 8 tj
Create a new HDL file File New VHDL File 9 tj
Create a new HDL file Note the default file name is Vhdl.vhd File Save As and give it an informational file name Change the file extension to vhdl (for VHDL files) Make sure Add file to current project is checked Note: New file is visible 10 tj
Set the Top Level Entity Right click on the design file in the Files window Select Set as Top Level Entity 11 tj
Enter your design 12 tj
Enter your design Counter_updn_n_bit.vhdl created 6/22/18 tj rev 0 n bit up/down counter example for showing a project from start to finish Inputs: rstb, clk, dir Outputs: bout[n-1:0] counts up when dir = 0 counts down when dir = 1 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Counter_updn_n_bit is generic( n: natural := 8 ); port ( clk: in std_logic; rstb: in std_logic; dir: in std_logic; bout : out std_logic_vector(n-1 downto 0) ); end entity; architecture behavioral of Counter_updn_n_bit is internal signals signal bout_sig: unsigned(n-1 downto 0); begin process(clk, rstb) begin reset if (rstb = '0') then bout_sig <= (others => '0'); rising clk edge elsif (rising_edge (clk)) then if(dir = '0') then bout_sig <= bout_sig + 1; else bout_sig <= bout_sig - 1; end if; end if; end process; Output logic bout <= std_logic_vector(bout_sig); end behavioral; 13 tj
Enter your design Create a component template for your design (DUT) Select File Create/Update Create VHDL Component Declaration Files from Current File Copyright (C) 2017 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. COMPONENT Counter_updn_n_bit PORT ( rstb : IN STD_LOGIC; clk : IN STD_LOGIC; dir : IN STD_LOGIC; bout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; Generated by Quartus Prime Version 17.1 (Build Build 590 10/25/2017) Created on Fri Feb 23 09:52:29 2018 14 tj
Elaborate Check the design syntax and create RTL Processing Start Start Analysis and Elaboration Fix all Errors These warnings are due to the fact that we included the QSF file even though we are not using this file for the DE10 Review all Warnings 15 tj
Verify the RTL Tools Netlist Viewers RTL Viewer b7 b6 b5 b4 b3 b2 b1 b0 1 + 1 1 1 1 1 1 1 0 1 Keep top 8 bits Effectively adds -1 Down - Subtractor Counter Register Up - Adder Up / Down Selector 16 tj
Flow MyDesign_tb.vhdl MyDesign.vhdl MyDesign_de10.vhdl 17 tj
Create Testbench File New VHDL File File Save As and give it an informational file name Note: New file is visible 18 tj
Enter your design 19 tj
Enter your design counter_updn_n_bit_tb.vhdl created: 3/17/18 by: johnsontimoj rev: 0 testbench for up down counter of counter_updn_n_bit.vhdl - library ieee; use ieee.std_logic_1164.all; entity counter_updn_n_bit_tb is generic( N: natural := 8 ); no port entry - testbench end entity; architecture testbench of counter_updn_n_bit_tb is signal CLK: std_logic; signal RSTB: std_logic; signal DIR: std_logic; signal BOUT: std_logic_vector((n - 1) downto 0); constant PER: time := 20 ns; Component prototype - component counter_updn_n_bit generic ( n : NATURAL := 8 ); port ( rstb : IN STD_LOGIC; clk : IN STD_LOGIC; dir : IN STD_LOGIC; bout : OUT STD_LOGIC_VECTOR((n - 1) downto 0) ); end component; - begin Device under test (DUT) DUT: counter_updn_n_bit generic map( n => N ) port map( clk => CLK, rstb => RSTB, dir => DIR, bout => BOUT ); - Test processes - Clock process clock: process begin CLK <= '0'; wait for PER/2; infinite: loop CLK <= not CLK; wait for PER/2; end loop; end process; Reset process reset: process begin RSTB <= '0'; wait for 2*PER; RSTB <= '1'; wait; end process reset; Run Process run: process begin initialize inputs DIR <= '0'; wait for reset wait for 2*PER; run code wait for (2**N)*PER; DIR <= '1'; wait; end process run; End test processes end architecture; 20 tj
Enter your design Elaborate the design With the original vhdl design set as the top level entity (not the xxxx_tb.vhdl design) Select Processing Start Start Analysis and Elaboration This causes Quartus to check the Test Bench code along with the original vhdl design 21 tj
Setup your simulation Use the ModelSim Testbench Setup notes as a guide 22 tj
Run your simulation Tools Run Simulation Tools RTL Simulation 23 tj
Verify your design Reset & Count up Wrap up & Count down Wrap down 24 tj
Flow MyDesign_tb.vhdl MyDesign.vhdl MyDesign_de10.vhdl 25 tj
Create DE10 implementation HDL File New VHDL File File Save As and give it an informational file name Note: New file is visible 26 tj
Set the Top Level Entity Right click on the design file in the Files window Select Set as Top Level Entity 27 tj
Enter your design 28 tj
- Enter your design counter_updn_n_bit_de10.vhdl created: 3/17/18 by: johnsontimoj rev: 0 DE10 implementation for up down counter of counter_updn_n_bit.vhdl Uses a 3 Hz clock divider, sw0 for reset sw1 for the dir input and LEDs for the count output - library ieee; use ieee.std_logic_1164.all; entity counter_updn_n_bit_de10 is port( CLOCK_50: in std_logic; SW: in std_logic_vector(1 downto 0); LEDR: out std_logic_vector(7 downto 0) ); end entity; architecture hardware of counter_updn_n_bit_de10 is signal CLK_SIG: std_logic; Intermediate clk signal Component prototypes component clk_3hz port( clk_50mhz : IN STD_LOGIC; rstb : IN STD_LOGIC; clk_3hz : OUT STD_LOGIC ); end component; component counter_updn_n_bit generic ( n : NATURAL := 8 ); port ( rstb : IN STD_LOGIC; clk : IN STD_LOGIC; dir : IN STD_LOGIC; bout : OUT STD_LOGIC_VECTOR((n - 1) downto 0) ); end component; - begin Device under test (DUT) CK: clk_3hz port map( clk_50mhz => CLOCK_50, rstb => SW(0), clk_3hz => CLK_SIG ); DUT: counter_updn_n_bit port map( clk => CLK_SIG, rstb => SW(0), dir => SW(1), bout => LEDR(7 downto 0) ); end architecture; 29 tj
Create a clock divider File New VHDL File File Save As and give it an informational file name Note: New file is visible 30 tj
Enter your design 31 tj
entity clk_3hz is port ( clk_50mhz : in std_logic; rstb : in std_logic; Enter your design clk_3hz.vhdl created 2/29/17 tj rev 0 50MHz -> 3Hz clock divider HDL Inputs: rstb, clk_50mhz Outputs: clk_1hz Notes: Typically this will be instantiated in a top level HDL for implementation on the DE10 board The 50 MHz clock input would be tied to CLOCK_50 the output clock would be tied to the clock inputs of the remainder of the design library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; clk_3hz : ); end entity; out std_logic architecture behavioral of clk_3hz is constants and parameters constant Tover2: signed(24 downto 0) := to_signed(8_333_332, 25); internal signals signal cnt: signed(24 downto 0); signal clk_out: std_logic; begin process(clk_50mhz, rstb) begin reset if (rstb = '0') then cnt <= Tover2; clk_out <= '0'; rising clk edge elsif (rising_edge(clk_50mhz)) then cnt <= cnt - 1; check if half way if (cnt < 0) then cnt <= Tover2; clk_out <= not clk_out; end if; end if; end process; Output logic clk_3hz <= clk_out; end behavioral; 32 tj
Compile Check the design syntax, create RTL, Place and Route Processing Start Compilation Check for timing issues Fix all Errors Review all Warnings 33 tj
Compile Check the Flow Summary Check success Correct Top Level Design Correct Part Number Check to make sure utilization makes sense 34 tj
Verify the RTL Tools Netlist Viewers RTL Viewer Clock divider Counter Correct I/O 35 tj
Flow MyDesign_tb.vhdl MyDesign.vhdl MyDesign_de10.vhdl 36 tj
Program the board Connect the DE10 board to computer Tools Programmer Point to the compiled output file xxxx.sof Start 37 tj
Verify Operation 38 tj