CS61C Summer 2015 Guerrilla Session 3: MIPS CPU Problem 1: swai (Sp04 Final): We want to implement a new I- type instruction swai (store word then auto- increment). The operation performs the regular sw operation, then increments the value in the rs register by 1. The RTL for the swai instruction is: Mem[R[rs] + SignExtImm] = R[rt]; R[rs] = R[rs] + 1; PC = PC + 4 a) Modify the single- cycle MIPS datapath (shown above), and describe your changes. Your modification may use simple adders, mux chips, wires, and new control signals. You may replace original labels where necessary. b) Fill out the values of the control signals in the table below, including any new control signals that you have added in part A. RegDst RegWr npc_sel ExtOp ALUSrc ALUctr MemWr MemtoReg 1
Problem 2: movz and movnz (Sp15 MT2) Consider adding the following instruction to MIPS (disregard any existing definition in the green sheet): Instruction movz rd, rs, rt movnz rd, rs, rt Operation if (R[rs] == 0) R[rd]ß R[rt] if (R[rs]!= 0) R[rd]ß R[rt] a) Translate the following C code using movz and movnz. Do not use branches. C code // a -> $s0, b-> $s1, c-> $s2 int a = b < c? b : c; MIPS slt $t0, $s1, $s2 b) Implement movz (but not movnz) in the datapath. Choose the correct implementation for (a), (b), and (c). Note that you do not need to use all the signals provided to each box, and the control signal MOVZ is 1 if and only if the instruction is movz. 2
c) Generate the control signals for movz. The values should be 0, 1, or X (don t care) terms. You must use don t care terms where possible. MOVZ RegDst ExpOp RegWr ALUSrc ALUCtr MEMWr MemToReg Jump Branch 1 This table shows the ALUCtr values for each operation of the ALU: Operation AND OR ADD SUB SLT NOR ALUCtr 0000 0001 0010 0110 0111 1100 3
Problem 3: Memory Access Optimization with rn, lbn & sbn (Su14 Final) We want to extend the familiar MIPS datapath to expedite memory operations such as memcpy, strcpy, memset, and such. We will implement 3 new R- Type instructions, all of which use counters to allow quickly scanning through memory values. We will use two 0- indexed counters named NL and NS, respectively for loads and stores. For sanity s sake, we will assume that $rd and $rt are never equal for this problem. Fill out the register transfer language (RTL) descriptions for these three operations. rn Instruction lbn $rd, $rt, ($rs) sbn $rd, $rt, ($rs) Resets both memory counters. Description Computes an address at NL offset from $rs. The contents of memory at this address are loaded into $rt. NL is stored into $rd. Then NL is incremented. Computes an address at NS offset from $rs. The contents $rt are stored into memory at this address. NS is stored into $rd. Then NS is incremented. rn Instruction RTL lbn $rd, $rt, ($rs) sbn $rd, $rt, ($rs) Before we implement these instructions, let s review how they work. Complete the strcpy MIPS code below to copy the string at address $a0 to address $a1 using only TAL MIPS instructions and these new instructions. Write only one instruction in each of the three blank lines. strcpy: rn 1 loop: 2 3 jr $ra Now, let s implement these instructions in the datapath. First, we want to implement counters for use in the datapath. We are going to base our counters off of simple registers that do not include enable or clear pins. Assume address is 32 bits, the register holds 32 bits, clock is the clock pulse, and control is some size less than 32 bits. Your counter implementation should support counter operations from all three instructions. Do not gate the clock! 4
We have the familiar single- cycle MIPS datapath, ready for modification to support these operations. To get you started, we have added a second register write port, and a new associated input rd, indicating that this register write port always writes to rd. Not counting the changes already made, list the most minimal set of changes to the following datapath diagram required to enable these three instructions. In this case, minimal refers to the number of added or modified components, as well as the number of added or modified control signal options. Please list one component addition or modification per line. For each change, list any new control signal that you might have introduced. You may not need all the provided boxes. Also draw your changes onto the datapath diagram. 1 2 3 4 5 New / Modified Component New / Modified Control Signal Fill out the control signals for each of these three instructions. List an explicit value for boolean values (0 or 1), list an X for don t cares, or list an intuitive name. For example: if you added a MUX, list the meaning of the selected input instead of the numeric value of the selector. Include all new control signals you have added. RegDst RegWr ALUSrc ALUCtr MemWr MemToReg rn lbn sbn 5
Problem 4: jals (Fa14 Final) Consider the following instruction: jals $rt $rs imm. The instruction stores PC + 4 in register $rt. At the same time, it sets the PC to the value in register $rs offset by the sign- extended imm value. a) Write the register transfer language (RTL) corresponding to jals: b) Change as little as possible in the 1- stage datapath below to support jals. In case of ties, pick the set of changes that maximizes the number of control signals that can be set to don t care. Draw your changes directly in the diagram and describe your changes below. You may only add multiplexers, wires, splitters, tunnels, adders, and add or modify control signals. Describe your changes: c) We now want to set the control lines appropriately. List what each signal should be, either by an intuitive name or {0, 1, don t care, multiply, etc.}. Include any new control signals you added. RegDst RegWr npc_sel ExtOp ALUsrc ALUctr MemWr MemToReg 6