REVISION ISTORY Revision Description Issue Date Initial Issue Jan. 09. 2012 0
FEATURES Fast access time : 55ns ow power consumption: Operating current : 45mA (TYP.) Standby current : 4 A (TYP.) S-version Single 2.7V ~ 3.6V power supply All inputs and outputs TT compatible Fully static operation Tri-state output Data byte control : B# controlled DQ0 ~ DQ7 UB# controlled DQ8 ~ DQ15 Data retention voltage : 1.2V (MIN.) Green package available Package : 48-pin 12mm x 20mm TSOP-I The AS6C1616 is a 16,777,216-bit low power CMOS static random access memory organized as 1,048,576 words by 16 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The AS6C1616 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The AS6C1616 operates from a single power supply of 2.7V ~ 3.6V and all inputs and outputs are fully TT compatible GENERA DESCRIPTION PRODUCT FAMIY Product Family Operating Temperatur e Vcc Range Speed Standby(ISB1,TYP.) Power Dissipation Operating(Icc,TYP.) AS6C1616(I) -40 ~ 85 2.7 ~ 3.6V 55ns 4µA(S) 45mA FUNCTIONA BOCK DIAGRAM PIN DESCRIPTION SYMBO DESCRIPTION A0 - A19 Address Inputs(word mode) A-1 - A19 Address Inputs(byte mode) DQ0 DQ15 Data Inputs/Outputs CE#, CE2 Chip Enable Input WE# Write Enable Input OE# Output Enable Input B# ower Byte Control UB# Upper Byte Control VCC VSS Power Supply Ground 1
PIN CONFIGURATION ABSOUTE MAIMUN RATINGS* PARAMETER SYMBO RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V Operating Temperature TA -40 to 85(I grade) Storage Temperature TSTG -65 to 150 Power Dissipation PD 1 W DC Output Current IOUT 50 ma *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. 2
TRUT TABE MODE CE# CE2 BYTE# OE# WE# B# UB# Standby Output Disable Read Write I/O OPERATION DQ0-DQ7 DQ8-DQ14 DQ15 igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z igh Z SUPPY CURRENT ISB,ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1 Byte# Read Dout igh Z A-1 ICC,ICC1 Byte # Write Din igh Z A-1 ICC,ICC1 Note: = VI, = VI, = Don't care. DC EECTRICA CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. *4 MA. UNIT Supply Voltage VCC 2.7 3.0 3.6 V Input igh Voltage VI *1 2.2 - VCC+0.3 V Input ow Voltage VI *2-0.2-0.6 V Input eakage Current II VCC VIN VSS - 1-1 µa Output eakage VCC VOUT VSS IO Current Output Disabled - 1-1 µa Output igh Voltage VO IO = -1mA 2.2 2.7 - V Output ow Voltage VO IO = 2mA - - 0.4 V Cycle time = Min. ICC CE# = VI and CE2 = VI II/O = 0mA - 55-45 60 ma Average Operating Power supply Current Other pins at VI or VI Cycle time = 1µs ICC1 CE# 0.2V and CE2 VCC-0.2V II/O = 0mA Other pins at 0.2V or VCC-0.2V - 8 16 ma ISB CE# = VI or CE2 = VI Other pins at VI or VI - 0.3 2 ma Standby Power Supply Current ISB1 CE# VCC-0.2V or CE2 0.2V Other pins at 0.2V or VCC-0.2V Notes: 1. VI(max) = VCC + 3.0V for pulse width less than 10ns. 2. VI(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(TYP.) and TA = 25 5. This parameter is measured at VCC = 3.0V SI *5 25-4 10 µa 40-4 10 µa SI - 4 40 µa 3
CAPACITANCE (TA = 25, f = 1.0Mz) PARAMETER SYMBO MIN. MA UNIT Input Capacitance CIN - 6 pf Input/Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse evels 0.2V to VCC - 0.2V Input Rise and Fall Times 3ns Input and Output Timing Reference evels 1.5V Output oad C = 30pF + 1TT, IO/IO = -1mA/2mA AC EECTRICA CARACTERISTICS (1) READ CYCE PARAMETER SYM. AS6C1616 UNIT MIN. MA. Read Cycle Time trc 55 - ns Address Access Time taa - 55 ns Chip Enable Access Time tace - 55 ns Output Enable Access Time toe - 30 ns Chip Enable to Output in ow-z tcz* 10 - ns Output Enable to Output in ow-z toz* 5 - ns Chip Disable to Output in igh-z tcz* - 20 ns Output Disable to Output in igh-z toz* - 20 ns Output old from Address Change to 10 - ns B#, UB# Access Time tba - 55 ns B#, UB# to igh-z Output tbz* - 25 ns B#, UB# to ow-z Output tbz* 10 - ns (2) WRITE CYCE PARAMETER SYM. AS6C1616 UNIT MIN. MA. Write Cycle Time twc 55 - ns Address Valid to End of Write taw 50 - ns Chip Enable to End of Write tcw 50 - ns Address Set-up Time tas 0 - ns Write Pulse Width twp 45 - ns Write Recovery Time twr 0 - ns Data to Write Time Overlap tdw 25 - ns Data old from End of Write Time td 0 - ns Output Active from End of Write tow* 5 - ns Write to Output in igh-z twz* - 20 ns B#, UB# Valid to End of Write tbw 45 - ns *These parameters are guaranteed by device characterization, but not production tested. 4
TIMING WAVEFORMS READ CYCE 1 (Address Controlled) (1,2) trc Address taa to Dout Previous Data Valid Data Valid READ CYCE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) Address trc CE# taa CE2 tace B#,UB# tba OE# tbz tcz toz toe to toz tbz tcz Dout igh-z Data Valid igh-z Notes : 1.WE#is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low, CE2 = high, B# or UB# = low. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high, B# or UB# = low transition; otherwise taa is the limiting parameter. 4.tCZ, tbz, toz, tcz, tbz and toz are specified with C = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tcz is less than tcz, tbz is less than tbz, toz is less than toz. 5
WRITE CYCE 1 (WE# Controlled) (1,2,3,5,6) twc Address taw CE# tcw CE2 tbw B#,UB# tas twp twr WE# twz TOW Dout (4) igh-z (4) tdw td Din Data Valid WRITE CYCE 2 (CE# and CE2 Controlled) (1,2,5,6) twc Address taw CE# tas twr CE2 tcw tbw B#,UB# twp WE# Dout twz (4) igh-z tdw td Din Data Valid 6
WRITE CYCE 3 (B#,UB# Controlled) (1,2,5,6) twc Address taw twr CE# tas tcw CE2 tbw B#,UB# twp WE# Dout (4) twz igh-z tdw td Din Data Valid Notes : 1.WE#,CE#, B#, UB# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#, B# or UB# = low. 3.During a WE# controlled write cycle with OE# low, twp must be greater than twz + tdw to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#, B#, UB# low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and twz are specified with C = 5pF. Transition is measured ±500mV from steady state. 7
DATA RETENTION CARACTERISTICS PARAMETER SYMBO TEST CONDITION MIN. TYP. MA. UNIT VCC for Data Retention VDR CE# VCC - 0.2V or CE2 0.2V 1.2-3.6 V Data Retention Current IDR S 25-2.5 10 µa VCC = 1.2V SI 40-2.5 10 µa CE# VCC-0.2V or CE2 0.2V S - 2.5 30 Other pins at 0.2V or VCC-0.2V µa SI - 2.5 40 µa Chip Disable to Data See Data Retention tcdr Retention Time Waveforms (below) 0 - - ns Recovery Time tr trc* - - ns trc* = Read Cycle Time DATA RETENTION WAVEFORM ow Vcc Data Retention Waveform (1) (CE# controlled) VDR Ù 1.2V Vcc tcdr tr CE# VI CE# Ù Vcc-0.2V VI ow Vcc Data Retention Waveform (2) (CE2 controlled) VDR Ù 1.2V Vcc tcdr tr CE2 VI CE2 Ø 0.2V VI ow Vcc Data Retention Waveform (3) (B#, UB# controlled) VDR Ù 1.2V Vcc tcdr tr B#,UB# VI B#,UB# Ù Vcc-0.2V VI 8
PACKAGE OUTINE DIMENSION 48-pin 12mm x 20mm TSOP-I Package Outline Dimension 9
ORDERING INFORMATION Alliance Organization VCC Range Package 1024K x 16 2.7V 3.6V 48pin TSOP I Operating Temp Industrial ~ -40 C - 85 C Speed ns 55 10