DATASHEET ALLEGRO DESIGN ENTRY HDL 610 ROBUST AND HIGHLY INTEGRATED SCHEMATIC DESIGN Cadence Allegro Design Entry HDL 610, a 600 series product within the Allegro system interconnect design platform, offers a schematic design entry and analysis environment. Its capabilities are integrated with extensive simulation (digital and analog) and board layout solutions. It serves as the productivity hub for all CAE-required tasks associated with system and high-speed design flow. While the methodology of schematic design has been simplified through several productivity-enhancing features, Allegro Design Entry HDL 610 streamlines the process at each stage of the design. Package design-in kit Interconnect models I/O buffer IP IC package design I/O buffer design The Allegro system interconnect design platform ALLEGRO DESIGN ENTRY HDL 610 Implement Design Explore Allegro Design Entry HDL 610 (DE-HDL 610) enables true concurrent engineering design practices to align with productivity improvements of Verify Virtual system interconnect model Specify PCB design Build Correlate IC design Silicon design-in kit On-target, on-time system interconnect design capture. When coupled with Allegro Constraint Manager, DE-HDL 610 expedites the design process by automating the communication of high-speed design requirements between engineers and CAD designers. THE ALLEGRO SYSTEM INTERCONNECT DESIGN PLATFORM The Cadence Allegro system interconnect design platform enables collaborative design of highperformance interconnect across IC, package, and PCB domains. The platform s unique co-design methodology optimizes system interconnect between I/O buffers and across ICs, packages, and PCBs to eliminate hardware re-spins, decrease costs, and reduce design cycles. The Allegro constraint-driven flow offers advanced capabilities for design capture, signal integrity, and physical implementation. With silicon design-in kits, IC companies shorten new device adoption time and systems companies accelerate PCB design cycles for rapid time to profit. Supported by the Cadence Encounter and Virtuoso platforms, the Allegro co-design methodology ensures effective design chain collaboration.
BENEFITS Highly integrated rules-driven design flow integrates with Allegro PCB Editor Integration with Allegro PCB Editor makes DE-HDL 610 the schematic editor of choice for designers who use Allegro PCB Editor for physical design. The Property Flow Editor allows you to configure which properties flow from the schematic to the board and which properties should be annotated back to the schematic from the board. Allegro Constraint Manager provides a unified environment for managing electrical constraints across the entire design flow By bridging DE-HDL 610, Allegro PCB Editor, Allegro Package Designer, and Allegro PCB SI applications, Allegro Constraint Manager presents constraints in a spreadsheet-like user interface for different types of electrical constraints. The manual task of identifying and managing differential signal pairs within the high-speed design flow has been automated. Differential pair signals are identified during schematic entry; constraints are then specified in Constraint Manager and controlled throughout the high-speed design flow. Designers can view and assign constraints or extended nets (Xnets) directly in Allegro Constraint Manager. Designers can assign SI models to components for use in high-speed interconnect simulation directly in Allegro Design Entry HDL. New Component Browser allows a very powerful interface for finding and searching for parts and is integrated with symbol and footprint viewers A quick pick bar allows easy access to frequently used components Supports team design, concurrent design, and a variety of design methodologies DE-HDL allows you to pick a methodology most suited to your design objectives from an array of possible options. From simple, conventional flat designs to complex designs with replicated blocks and associated layouts, DE-HDL supports all design methodologies. Updated commands to insert or delete sheets simplifies page renumbering. Offers comprehensive and customizable design rule checking with the Rules Checker option The Rules Checker option helps you avoid multiple design iterations. It allows you to perform electrical and design rule checks to verify drafting standards, and correct property names, syntax, and values. Rules Checker also includes checks to support downstream simulation and PCB processing. Design reuse capabilities leverage the maximum benefit from existing designs. Ability to insert sheets from other designs (with checks for shorts) allows reuse of parts of the design which may not have been captured as blocks With DE-HDL, you can store complete schematics associated with Allegro PCB Editor as cells in libraries. You can use these cells in other designs similar to other components. Design teams can leverage the work invested in reusable blocks by storing them in libraries for immediate use. A COMPLETE, ENTERPRISE- LEVEL DESIGN CAPTURE SOLUTION FLEXIBLE DEPLOYMENT Allegro Design Entry HDL is designed to facilitate deployment in an enterprise environment, where multiple designers can use the same installation and libraries. This facilitates new release management and sharing of custom utilities developed onsite. DE-HDL allows localization at three levels: installation, user, and project. This provides for a controllable yet flexible design environment for the designers across the enterprise. DE-HDL is available on UNIX (Solaris, HP, IBM), Windows (2000/XP Pro), and Linux platforms, and the design data can be transferred across platforms without any translation. The license floats between platforms for maximum flexibility. 2
TEAM DESIGN, CONCURRENT DESIGN DE-HDL maximizes workflow efficiencies through its collaborative design approach. The design can be partitioned at a sheet or block level, and each designer can be assigned one or more blocks or sheets. Any number of designers can work on different parts of the same design simultaneously without interfering with each other. The various design stages can then be combined before proceeding to the layout in Allegro PCB Editor. This concurrent design approach makes DE-HDL extremely productive for large designs. Designers work on the board layout and schematic in parallel. Changes made in either DE-HDL or Allegro PCB Editor can be merged and synchronized periodically. For example, if the PCB layout designer adds or changes a termination resistor or bypass capacitor in the board layout, design synchronization can be used to update the schematic. The design synchronization feature compares the schematic and the board layout, producing a hierarchical ECO report that automatically updates the chosen document, even adding the new terminators to the schematic if required. The ability to store the version history of schematics allows more efficient team design. LIBRARY DEVELOPMENT AND MANAGEMENT The Part Developer included with DE-HDL makes it easier to create and validate different views of the part used in a design flow. It provides an intuitive user interface to split large pin-count devices into multiple schematic symbols. Part Developer also scales upward into Allegro PCB Librarian 610, a streamlined solution for creating and managing enterprise libraries. As an add-on option, Librarian streamlines Comprehensive and intuitive part creation allows you to quickly create parts that are complete, correct, and verified in the design flow and automates the manual tasks librarians face using Part Developer to manually create, validate, and manage part libraries. It also provides a utility to import XML datasheets to create complete DE-HDL parts or to translate complete OrCAD Capture design entry parts into DE-HDL. It is now possible to track changes in versions of library parts used in a design using the version differences UI. CUSTOMIZABLE RULE CHECKING DE-HDL helps you avoid multiple design iterations with the Rules Checker option, a truly comprehensive verification facility. It allows you to perform electrical and design rule checks to verify drafting standards and correct property names, syntax, and values. Rules Checker also includes rules to support downstream processing, fan-in and fan-out errors, load errors, power requirements, and cost requirements. Rules Checker checks the alignment between logical and physical designs. In addition, it lets you define custom rules to ensure conformity to design requirements specific to your company or your projects. The rules in Rules Checker are written using the advanced rule language (ARL), which is a high-level LISP-like rule development language. Rules Checker can be used for schematics, symbols, and the physical netlists. It has a rule development and debugging environment for defining rules and can run in batch mode, facilitating deployment in an enterprise environment. INTEGRATED WITH CRITICAL DESIGN TECHNOLOGIES ALLEGRO SI SIMULATION INTEGRATION To facilitate simulation of high-speed nets, schematic designers can validate and assign signal integrity models to components. The model assignment UI allows engineers to assign models to validate model interfaces at the time of assignment. In addition, engineers can auto-generate models for discrete components. Using the SI models assigned, it is possible to define extended nets (Xnets) and assign constraints to Xnets using Constraint Manager. Users can view and control the routing topology nets using the topology editor. Simulating nets with SI models helps engineers assign constraints suitable to the physical design being considered. The ability to simulate interconnects and assign constraints in parallel significantly reduces the labor required to ensure that designs work the first time. It also allows outsourcing of the physical design, as all constraints can be captured and passed through the system after verification. ALLEGRO CONSTRAINT MANAGER INTEGRATION Allegro Constraint Manager provides a unified environment for managing high-speed electrical constraints through the PCB design flow, encompassing DE-HDL, Allegro PCB Editor, Allegro Package Designer, and Allegro PCB SI 610. Constraint Manager presents constraints in a spreadsheetlike interface with separate worksheets for different types of electrical 3
constraints. It allows the user to capture, manage, and validate the different rules in a hierarchical fashion. Constraint Manager enables designers to group all of the highspeed constraints for a collection of signals to form an electrical constraint set (ECSet). This ECSet is then associated with all the nets in the group. For example, if the same set of constraints is applied to all bits of a 256-bit bus, you can define the constraint once in an ECSet and then associate all the bits of the bus with that ECSet. This makes management of changes in the ECSet easier. The flexibility of Allegro Constraint Manager allows users to override constraints in specific cases. You can continue adding constraints as attributes on the DE-HDL schematic. Constraints entered in the schematic are automatically transferred to the Constraint Manager user interface. Constraint Manager is integrated with both DE-HDL and the physical design tools, making it easy to capture and manage constraints during the logical design phase. Users can utilize these constraints during the physical design phase as well. All constraint information is stored in the schematic database, passed to the board, and kept in sync, which enables design teams to work in either environment concurrently. At any point during the design phase, designers can launch the Constraint Manager to add, view, and manage high-speed constraints in formation. The constraints are then synchronized to design entry in DE-HDL, interconnect exploration and simulation in Allegro PCB SI, and physical PCB layout and design validation in Allegro PCB Editor. This ability to combine automatic and manual constraint definitions is ideal for high-speed designs. As the rules are embedded in the design, the designer can concentrate on optimizing the physical layout for size, routability, and manufacturability, while the software automatically communicates compliance with the engineer s performance requirements. The manual task of identifying and managing differential signal pairs within the high-speed design flow has been automated. Differential pair signals are identified during schematic entry, and constraints are specified in Constraint Manager and controlled throughout the high-speed design flow. INTEGRATION WITH ALLEGRO PCB EDITOR AND ALLEGRO PACKAGE DESIGNER The integration of DE-HDL with Allegro PCB Editor makes it the schematic editor of choice for all designers looking to increase productivity. The Property Flow Editor allows you to configure which properties flow from the schematic to the board and which properties should be annotated back to the schematic from the board. In addition, the flow automatically takes care of backannotation of pin, section, and component swapping in Allegro PCB Editor to DE-HDL. Two-way cross-probing between Allegro PCB Editor and DE-HDL allows you to locate components in the schematic by highlighting the component in Allegro PCB Editor and vice versa. To help in the placement phase, you can place components in Allegro PCB Editor by selecting the components in DE-HDL. You can also place all components on a DE-HDL page in a single step in Allegro PCB Editor. This ability is useful when a component and all discrete elements associated with it are on one schematic page. Using design differences, you can compare schematics and boards before transferring design information in either direction. With design association, you can backannotate terminators and bypass capacitors added directly to the board to the schematic. This allows logic design and signal integrity design to proceed in parallel. If you elect to use digital simulation using Verilog simulator or VHDL to verify functionality, then you can use the SDF file generated from Allegro PCB Editor to run post-routing simulation to factor board interconnect delay. Designers can automatically synthesize thick and thin film resistors in Allegro Package Designer by configuring the DE-HDL schematic and Allegro Package Designer. When you or your team moves from one release of DE-HDL/Allegro PCB Editor to the next, you gain access to capability enhancements in the design flow rather than tool enhancements in different tools. In addition, you ll enjoy the benefit of using a flow that is validated within Cadence before release. The Allegro Physical Viewer included with DE-HDL lets you view the Allegro PCB Editor. This is beneficial for viewing ECOs and other documentation-related issues. DIGITAL SIMULATION FLOW The HDL-centric architecture of DE-HDL provides a seamless integration with Verilog and VHDL simulators. When a design in DE-HDL is saved, Verilog and VHDL code are automatically generated from the design data and used in all downstream tasks within a design flow. DE-HDL is fully integrated with Cadence NC Verilog and NC-VHDL simulators. The same DE-HDL schematic drives both logic simulation and layout. Other schematic tools require you to create separate versions of designs for simulation and PCB layout. DE-HDL generates an HDL simulation code that automatically handles discrete components like pull-ups, terminators, and bypass capacitors. The configurable simulation capabilities of DE-HDL allow you to map different models to blocks, schematics, and components for simulation at different levels of abstraction and easily switch between these levels using configurations. This is useful in top-down system design where the design may first be simulated at a behavioral level before the creation of schematics for the blocks. By comparing the simulation results at the behavioral correctness of the design can be verified. It is possible to mix the blocks that only have behavioral models with the blocks that have completed schematics during the logic simulation phase. You can cross-probe between the components on the HDL netlist and the schematic for easy debugging for simulation results. The digital simulation flow also supports the use of Synopsys SMART models. 4
Tight integration with Allegro AMS Simulator lets you perform analog simulation and debugging within the Allegro Design Entry HDL environment ANALOG SIMULATION FLOW DE-HDL is tightly integrated with Allegro AMS Simulator 210 for fluid analog simulation. You can configure schematic symbols to reference Spice simulator models and simulate the design from within the DE-HDL environment. You can also cross-probe between schematic and simulation environments to quickly locate and characterize design bugs. This provides a reliable, low-cost analog simulation and verification solution for DE-HDL customers on the Windows platform. At the other end of the spectrum, Analog Workbench provides a highend comprehensive analog design environment that is integrated with DE-HDL only on the UNIX platform. DESIGNING RF CIRCUITS Many of today s digital PCB systems include some circuitry that operates at radio frequencies. These blocks have special design requirements and are predominantly designed and simulated with Agilent ADS (formerly Agilent EEsof). However, this block needs to be present on the same board along with other digital and analog circuitry. To enable this, DE-HDL and Allegro PCB Editor provide a flow to import RF blocks designed in Agilent ADS into the Cadence board design flow. Allegro PCB Editor and DE-HDL can automatically import the ADS physical layout and schematic through a robust IFF interface. Once imported, the ADS design behaves like a module, with its components mapped to Allegro PCB Editor library parts. The imported module can be locked to prevent editing or unlocked to allow editing. Even if locked, the module still allows you to connect it with the rest of the design and assign constraints to the nest connected to the block. FPGA FLOW DE-HDL provides a comprehensive FPGA design solution and is integrated with Synplify, Xilinx, Actel, and Altera. DE-HDL supports both major design practices followed in the industry. The initial design with FPGAs and board layout are designed by different teams, although the work proceeds in parallel. After the FPGA is designed by the FPGA team, the board design team places the FPGA symbol on the board schematic and uses this for the board design process. To support this practice, DE-HDL provides the Build Physical Wizard, which allows you to import Xilinx, Actel, and Altera FPGAs into the DE-HDL 610 schematic and automatically creates the files required to drive Allegro PCB Editor, DE-HDL, and the digital simulation flow. DE-HDL also intelligently manages the interface to the FPGA so that the board schematic has to change when the FPGA pin assignments change, but the design does not change logically. Updates are made to the flow to ensure synchronization to the latest FPGA vendor releases. This ensures that a designer is using the most recent version of the vendor s software and devices for implementation within their PCB design process. Another common practice is when the same team that designs the schematic designs the FPGAs. To support this practice, DE-HDL allows teams to design the FPGA using a schematic (primitives supplied by the FPGA vendor) or using Synthesis with Synplify. The integration with Synplify allows you to capture your board design with behavioral descriptions of the FPGAs and ensure correct system behavior before synthesizing the FPGA and mapping to a FPGA from Xilinx, Actel, or Altera. After mapping, DE-HDL allows you run post-route simulation of the FPGAs. This flow is tightly integrated with the DE-HDL digital simulation flow using the NC-Verilog and NC-VHDL simulators. The high level of integration between DE-HDL, Synplify, logic simulators, and FPGA vendor software allows you to concentrate on the design and leave the infrastructure issues to the flow. 5
Allegro Design Entry HDL 1. Design schematic block 2. Import logic 3. Physical layout 4. Create module Allegro PCB Editor re-enter the design or create (and maintain) multiple copies of it scattered throughout different design databases. Because the data defining reusable modules is maintained and updated in both logical and physical design databases, designers can place the modules during either schematic capture or layout. This is extremely useful when the same section, like a power supply, is used in multiple designs. 6. Save block 5. Backannotate properties Allegro Design Entry HDL supports full reuse of PCB layout data for hierarchical blocks, increasing reliability and saving time FLEXIBLE DESIGN FLOWS AND METHODOLOGIES DE-HDL allows you to select the methodology most suited to your design objectives from an array of possible options. From simple conventional flat designs to complex designs with replicated blocks and associated layouts, DE-HDL supports all design methodologies. FLAT DESIGNS AND HIERARCHICAL DESIGNS Flat designs are conventional singlelevel designs that run into hundreds of pages. DE-HDL allows multiple engineers to work together even on flat designs and reuse sheets from existing designs. This methodology, however, does not allow the user to exploit all the powerful features of the DE-HDL Allegro PCB Editor flow. DE-HDL allows you to import parts of other designs into your current design, making it easy to build newer product versions. With its ability to import sheets or blocks from other designs, DE-HDL is valuable for both flat and hierarchical designs. DE-HDL supports both top-down and bottom-up methodologies for hierarchical design. A top-down methodology is where a block level schematic of the design is created first and then each sub-block is designed. A block can be a flat schematic or consist of other hierarchical blocks. A bottom-up methodology is where the lower level schematics are created first and the higher level blocks, which capture the system behavior, are generated later. It s possible to automatically create block representation of the schematic along with HDL descriptions for Verilog and VHDL. You can also complete a highlevel system simulation before detailed schematics are done by generating schematic blocks from high-level HDL descriptions and wiring them together using the DE-HDL simulation interface. A mix of the two approaches can also be followed. In any case, the different blocks can be flat schematics or consist of other blocks. Different designers can design the blocks separately if required. The design can have multiple levels of hierarchy. DE-HDL will ensure that reference designators remain unique and nets do not short accidentally. DE-HDL also provides the user with powerful features for design navigation and query. For maximum benefit,each block can be packaged separately; a layout can be associated with each block and combined together later. Using this methodology, different layout engineers can work on the layout in parallel, thus saving time (which is not possible in the case of flat designs). DESIGN REUSE DE-HDL allows you to store complete schematics with associated Allegro PCB Editor layouts as cells in libraries. You can use these cells with standard parts to facilitate design capture. Design teams can leverage the work invested in useful blocks by storing them in libraries and using them repeatedly. This saves the effort required to REPLICATED HIERARCHICAL BLOCKS At times, the same block may be used multiple times in the same design. DE-HDL allows you to place the block as often as you like in the design while maintaining just one copy of the underlying schematics. This makes change management easy. At the same time, it allows the designer to annotate different properties on the components and nets within each instance of the block. For example, if you have a 16-channel oscilloscope to design, you need to design a block that will be replicated 16 times. You need to create only one schematic and block and place the block 16 times in your design. Changes made in the schematic of the block automatically propagate to all the 16 instances simultaneously. It s also possible to lay out this block just once in Allegro PCB Editor and place the complete block layout in Allegro PCB Editor 16 times. The time and effort saved by this capability is enormous. VARIANT DESIGN Designers can conserve even more time and effort at the structural level by exploiting DE-HDL support of design variants. Suppose you need to create slightly different versions of the same basic design for example, to offer graduated performance levels to different market segments, or to address varying regional requirements. In the past, this meant making complete copies of the original design for every variant, making the minor changes required in each, and then trying to maintain them all without getting them mixed up or forgetting to update them all when an ECO to the common logic was necessary. 6
DE-HDL cuts straight through this problem. It enables you to derive variants of a single base design by assigning alternate sets of attributes to the components, wires, or other elements of the design. An ECO applied to the base design automatically propagates to all its variants. The DE-HDL user interface makes it simple to view or plot specific variants. POWERFUL SCHEMATIC DESIGN FEATURES Allegro Design Entry HDL provides powerful schematic design features that make it easy to design complex schematics. PARAMETERIZATION DE-HDL allows you to parameterize a block or a component as required instead of placing them multiple times on your schematic. For example, if there is a 512-bit bus, a user need only place one resistor on the bus, and use a SIZE parameter value of 512. All individual bits will be connected to the resistor in the physical netlist, greatly reducing the number of graphical components needing to be displayed within a design. The use of a SIZE property with a component during design entry simplifies the creation and graphical viewing of a schematic while ensuring connectivity to a bus. Similarly, if you want to duplicate the same value for a particular parameter among a group of components, you can specify the value within a single component and automatically update the value in all remaining components. DE-HDL allows you to specify properties on blocks and have them inherited by all the underlying components in a controlled manner. SPLIT INSTANCES Some large components have a few thousand pins. It s not possible to show them all on a single schematic page. DE-HDL allows you to split as many different symbols as you like and to have important pins shown on every symbol if required. These symbols can be placed on different sheets of the design and will get packaged into a single physical device on the board. The HDL netlist treats this as a single part so you can have a flat Verilog file for simulation though the part is split into multiple symbols. SKILL AND CAE VIEWS Designers can write SKILL programs to customize DE-HDL and create custom commands. The custom programs can be used for querying and modifying the design data in DE-HDL schematic sheets. By placing these programs in a common area, it s possible for a team to share the efforts of all team members. CAE Views is a C language API for DE-HDL that can access the design at a logical level or access the physical netlist. You can write C programs to process design using this API, including custom netlists. GLOBAL NAVIGATE, GLOBAL FIND AND REPLACE Whether you re using a flat design with a few hundred sheets or a hierarchical design with multiple levels of hierarchy, Global Navigate allows you to navigate to any net or part in your design with a few mouse clicks. The dockable Global Find and Replace window allows you to find and replace parts or properties across the design. These can be highlighted directly from Allegro PCB Editor or Allegro PCB SI. PART TABLE FILES Part Table files allow you to map different physical parts to the same schematic symbols. There might be a few thousand different resistors in your design. You do not have to create a separate schematic symbol for each part view. You can map multiple physical parts (with different footprints if need be) to the same symbols and reference them uniquely using the attributes of the part such as value, tolerance, wattage, etc. This allows you to reduce investment in libraries at the same time it allows you to quickly modify your design by manipulating properties. DE-HDL works with Allegro PCB Editor to make sure all correct parts get selected and placed in the design. Part Table files can now be launched directly from the Part Browser by adding a property in the attribute form. By clicking on the associated URL, the Part Browser launches with the data from the Part Table file. These properties and values can be locked to prevent accidental modifications. Part Manager is a new tool that verifies which parts in a design match the library parts in the Part Table files. This solution ensures that designs are kept intact when corporate part tables are modified. DATA MANAGEMENT DE-HDL has built-in data management capabilities for schematics using Version sync, which is included in DE-HDL 610. SCRIPTS AND NON-GRAPHICAL MODE Users can write DE-HDL scripts for frequently used actions and run these scripts on the design. It is also possible to run DE-HDL in a non-graphical mode, in which scripts can run without user intervention and without taking up valuable real estate on the display. This is used frequently for automation purposes. CUSTOMIZATION AND UTILITIES Allegro Design Entry HDL provides many tools that complete the toolset and add value to the overall flow. Clicking on a node of the design flow graphic launches the appropriate tool for that phase of the design process 7
The design flow is rendered in HTML you can customize it to meet your particular design flow requirements CROSS REFERENCER The cross referencer annotates the schematic with references to allow easy tracking of signals on plotted schematics. This is used widely in test and manufacturing. The cross referencer can handle all kinds of flat hierarchical designs and produce outputs with reference to the hierarchy or the design sheet number. This is highly customizable and can produce a wide range of reports for documentation. BILL OF MATERIALS (BOM) GENERATOR DE-HDL gives you fine-tuned control over BOM creation, ensuring parts lists that meet your needs precisely and contain everything necessary for manufacturing. You can generate a BOM for a base design or any of its variants, list non-electrical parts in a callout file, and have DE-HDL merge them in the BOM with the electrical parts from the schematic. You can associate electrical and non-electrical parts in the schematic for example, a heatsink with an IC and have that association shown in the BOM. You can output the BOM in ASCII text, spreadsheet, or HTML format as needed to optimize transmission to manufacturing and other recipients. ARCHIVER Achiver is extremely useful when you are done with the design and want to file it for future use, or when you want to take the design home where you may not have access to all libraries. The archiver copies all the cells in the design into a local library so that you can work without access to corporate libraries and be immune to changes in libraries as long as you are working on the archive. ELECTRICAL RULE CHECKS AND NETLIST REPORTS Built-in electrical rule checks and netlist reports can be generated for documentation and verification purposes. CUSTOM VARIABLE SUPPORT Maintaining project name, designer, and other such data on schematics has always been time consuming and error prone. Often, this requires either a custom page border or manual updating for each schematic page. DE-HDL streamlines and systemizes this work by allowing you to attach custom text with dynamically updated variables to schematic objects. An extensive set of predefined variables, plus the ability to create user-defined variables, enables you to implement your company s documentation standards in an efficient, uniform manner. ALLEGRO PROJECT MANAGER Allegro Project Manager allows you to create projects, and manage setup information for all tools in the flow, and it provides an interface to launch the tools used in your design flow, such as DE-HDL, Allegro PCB Editor, and Allegro PCB SI. Cadence supplies two flows by default: the board design flow and the FPGA design flow. Project Manger allows you to change the setup to launch other tools you use and since this is HTML based, you can create your own flows in HTML and use them if you so prefer. The Project Manager keeps track of all the tools launched and their status and facilitates inter-tool communication. EDIF 300 DE-HDL has an interface to export and import EDIF 300 netlists. This version of EDIF is commonly used for customization of schematic design data with testing or manufacturing equipment. DE-HDL interfaces to other types of EDIF requirements as supported by add-on options supplied by E-tools Corporation. Productivity boosters DE-HDL simplifies the identification and tracking of differential signal pairs and associated constraints initiated during schematic design, and it adheres to these properties throughout the high-speed design process Global Find and Replace allows design changes within a hierarchical design module or manages specific sheets to process across a flat design Dockable Design Viewer simplifies the hierarchical or cross-sheet traversal of schematics and manages the order of design and sheet plotting The power pin signal assignment utility automates manual reassignment of power and ground connectivity commonly needed for large pin count devices Customizable user interface offers optional command-line entry, menus, and keyboard toolbars Point-to-point connection router draws wires fast Automatic insertion of a two-pin component within an existing net, automatically generates associated input and output pins while adhering to the associated net names User-defined mouse strokes allow you to execute single or multiple commands directly from within the canvas without using the toolbar, menus, or console Function keys streamline design entry tasks by mapping complex or frequently used commands to a single key 8
Pre-select or post-select option associates command usage with noun-verb or verb-noun paradigm Enhancements to the attribute form allow commonly used properties to be automatically seeded with corresponding property values Copy/Paste within and between designs Named Viewports Navigation toolbars for error/warning messages OPERATING SYSTEM SUPPORT Red Hat Linux 7.3, 8.0, RHEL 3.0 Windows 2000 with Service Pack 4, XP Professional Sun Solaris 7, 8, 9 HP-UX 11.0, 11.11i IBM AIX 5.1 CADENCE SERVICES AND SUPPORT Cadence application engineers can answer your technical questions by telephone, email, or Internet they can also provide technical assistance and custom training Cadence certified instructors teach over 70 courses and bring their realworld experience into the classroom Over 25 Internet Learning Series (ils) online courses allow you the flexibility of training at your own computer via the Internet SourceLink online customer support gives you answers to your technical questions 24 hours a day, 7 days a week including the latest in quarterly software rollups, product change release information, technical documentation, solutions, software updates, and more Allegro Design Entry HDL Feature Set Efficiency 210 610 Logical/physical design reuse Support for design variants Point-to-point routing Pin-to-pin wiring Mouse stroke shortcuts Component insertion with auto-connection Connectivity tracing Hierarchical design Hierarchical block support; automated connectivity with subordinate logic Hierarchical plotting HDL support Create parts from HDL descriptions Generate HDL description from schematic Part creation (1) Part Development Wizard Symbol partitioning Design verification Standard design and electrical rule checks Rules Checker option for user-defined checks Part manager Customization SKILL scripting language for custom key definitions, commands, and utilities Graphical user interface customization Custom text and variables for consistent, easily maintained schematic documentation Inter-tool integration Allegro Constraint Manager Allegro Viewer Data sharing with Allegro PCB Editor, NC-VHDL simulator, Allegro Package Designer, and Allegro PCB SI IFF import from AgilentADS Ability to add properties that specify removing or shorting parts for digital simulation Ability to map simulation models to schematic symbols Data sharing with Allegro AMS Simulator 210 Cross-selection, cross-probing between logical, physical, simulation environments Bi-directional logical-physical annotation Logical-physical comparison view/report Output Automatic HDL netlist generation Custom netlisting BOM in multiple formats BOM for design variants BOM including non-electrical parts, optionally correlated to associated electrical parts EDIF 300 Design process management Built-in version control utility Component Revision Manager Concurrent engineering Project Manager FOR MORE INFORMATION Contact Cadence sales at 1.800.746.6223 or visit www.cadence.com for additional information. To locate a Cadence sales office or value-added reseller (VAR) in your area, visit www.cadence.com/contact_us. 2005 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, NC-Verilog, OrCAD, SourceLink, Verilog, and Virtuoso are registered trademarks, and Encounter is a trademark of Cadence Design Systems, Inc. All others are properties of their respective holders. 4429E 06/05 9