FPGA ADVANTAGE FOR HDL DESIGN

Transcription

1 FPGA ADVANTAGE FOR HDL DESIGN

2 A STREAMLINED S OLUTION FOR FPGA DESIGN The FPGA Advantage Design Solution gives you smooth data transition from one step of your design process to the next. All steps are linked, enabling fast, efficient debugging. Plus, the FPGA Advantage management system ensures consistent data files and versioning. The FPGA Advantage Design Solution from Mentor Graphics delivers an integrated and easyto-use solution for creating, verifying, synthesizing, documenting, and managing FPGA design. Braiding together the proven capabilities of HDL Designer Series for design creation, documentation, and management, ModelSim for simulation, and LeonardoSpectrum for synthesis, FPGA Advantage provides an HDL design methodology that delivers an incomparable increase in productivity you can debug the way you design. True integration delivers more design in less time FPGA Advantage is not a mere assemblage of three existing point tools. It represents a unique design flow truly integrated to provide seamless and streamlined execution. This tight integration ensures smooth data flow from one step to the next, plus all the steps are linked to make debug an efficient exercise. The FPGA Advantage Design Solution is multiplatform and multi-language capable, allowing FPGA Advantage to work in UNIX, Windows, NT, and environments of VHDL, Verilog, or mixed- HDL language code.

3 A PICTURE S W ORTH A T HOUSAND W ORDS Full text user support FPGA Advantage provides highly productive methods for creating text-based HDL designs, enhancing your productivity by smoothing the assimilation of intellectual property (IP), previously designed blocks, and newly written HDL code. Interface-Based Design (IBD ) a new patentpending tabular design entry method simplifies the definition of interconnects for large, complex, FPGA designs. IBD s easy-to-view, compact, tabular format displays the design structure, automatically generates the HDL netlist, and enables easy documentation. The Tabular I/O and Block Diagram editors complement both the IBD and your text editor by simplifying the interface definition of several hundred port modules displaying a picture representation of the IBD. Graphic representations simplify and illuminate new and legacy designs Graphics enable easy detection of bugs and quick alteration of designs. You can rapidly create, modify, debug, and document sophisticated HDL designs with real-time syntax and semantic verification. When graphically debugging, you are able to step through lines of code, step optionally over subroutines, or step into the next graphical object. All changes in states are color-coded to ease in following the flow of logic while debugging. Not only can you create new designs with FPGA Advantage, you also have the ability to reuse previous designs and design blocks. With some offerings of FPGA Advantage, you can read in existing VHDL or Verilog text files and create block diagrams, state machines, flow charts, or Interface-Based Design descriptions. With HDL2Graphics, FPGA Advantage can convert an entire HDL design into a hierarchical design database. You can import and understand IP blocks or legacy code even partial or incomplete designs through a graphical representation. The various levels in the hierarchy correspond to block diagrams, state diagrams, flow charts, text files, and IBDs. You are able to edit all of the graphics, including those from recovered designs, providing design teams with the productivity gains of design reuse. Reuse for the future Using FPGA Advantage prepares your design for the next generation automatically. All documentation is linked to your graphical representation. In other words, you re already set to go for your next design.

4 R EAP THE P OWER AND A GILITY OF I NTEGRATION Front-to-back cross-referencing provides an intuitive way to interactively link graphics, HDL text, warnings and errors, simulation windows, and synthesis results. Design Browser environment a powerful timesaver The Design Browser shows objects in a highly condensed form for a wide look at the entire design. With the Design Browser as project manager you can execute all steps of the design process. Design Flow buttons make the HDL design flow fast and intuitive. FPGA vendor IP Xilinx CORE Generator and Altera MegaWizard interfaces provide seamless integration between FPGA Advantage and the vendors IP. These vendor cores slide directly into the FPGA Advantage design environment, hastening the design construction and facilitating management of the design area and timing budgets. Animated simulation speeds analysis Dynamic animation the ability to view simulation effects directly on the graphical diagrams reveals high-level design and functional behavior, enabling design teams to debug at the same level the design was entered. Encapsulated place and route FPGA Advantage encapsulates place and route. Intelligent place and route script files can be automatically generated to enforce customized design flows throughout the company, resulting in better circuit implementations. Unsurpassed vendor support and integration FPGA Advantage supports/integrates with all major FPGA vendors, ensuring your design is accurate and up-to-date. A complete list can be found at Library portability and support Wide library support contributes to the superior FPGA Advantage Design Solution. Since your design is portable across multiple platforms, only one library format needs to be maintained, saving time and ensuring up-to-date support. Log window manages messages For ease of management, FPGA Advantage offers a log window for reporting actions completed, warnings, and errors. Warnings and errors are color-coded for easy recognition and, when selected, are crossreferenced to the originating graphic and HDL source code. Documentation made easy Documentation is an essential part of the design process. Without it, the information of the design cannot be communicated and reuse of the design is difficult in the future. FPGA Advantage supports OLE, postscript, and HTML export for documentation needs, making documentation easier and encouraging it throughout all design development phases. Incremental HDL generation, compilation, and synthesis Small changes to a design may be very time consuming. FPGA Advantage takes an incremental and automatic approach to all iteration actions, advancing the designer to the next design activity rapidly and efficiently. HTML Export assists in design communication making documentation easier.

5 T HE T ECHNOLOGY AT THE C ORE OF FPGA ADVANTAGE Design management FPGA Advantage provides hierarchical control of your design using embedded blocks. When issued the simulate command, FPGA Advantage automatically generates and recompiles only those design units and dependencies that have been changed, creating a fast, more efficient route from design changes to a compiled database. Organize and simplify complex ideas FPGA Advantage can handle thousands of HDL files. Configuration management, and design management with version control, are achieved through Revision Control System (RCS), Gnu Concurrent Version System (CVS), ClearCase from Rational, Visual SourceSafe from Microsoft, or DesignSync from Synchronicity. Unsurpassed simulation FPGA Advantage delivers leading compiler/simulator performance, complete freedom to mix VHDL and Verilog, and the unmatched ability to customize the simulator. You have access to many advanced technologies such as Direct Compile for the fastest compile times, Tcl/Tk technology for a customizable user interface, and Single Kernel Simulation for mixing VHDL and Verilog. Complete FPGA design cycle from entry to place-and-route verification is attained with an easy push button flow. (All major FPGA vendors supported.) Proven synthesis FPGA Advantage lets you embrace a hierarchicalbased, block-level design approach for synthesis. With a proprietary F.A.S.T. (FPGA Architecture Specific Technology) algorithm, FPGA Advantage delivers the highest quality of results. It includes a unique incremental design process that reduces the time required to design million-gate FPGAs by as much as thirty percent. TimeCloser technology New TimeCloser technology, along with FPGA vendor tool integration, allows the designer to break down the wall between synthesis and place and route. The design, with all constraints, is seamlessly transitioned to the back end place-and-route environment of the FPGA vendor tool.

6 A SOLUTION FOR E VERY D ESIGNER Three versions of FPGA Advantage provide price and performance flexibility Because design needs vary, FPGA Advantage is available in three versions. FPGA Advantage for Personal HDL Design provides the right amount of power for the individual designing an FPGA, and FPGA Advantage with Personal Simulation increases the control of design management and documentation capability. FPGA Advantage for HDL Design delivers all the added features for complex FPGA design teams. All FPGA Advantage offerings are available with VHDL, Verilog, or mixed-hdl language support and come with text-based design editors, graphical editors, or both sets of editors (Pro). FPGA Advantage for Personal HDL Design and FPGA Advantage with Personal Simulation offer the choice of Level 2 or Level 3 synthesis control and are available on Windows platforms. FPGA Advantage for HDL Design is available on both Windows and Unix platforms and includes additional gate-level debugging functionality. Software Language Design Tools Support Editors Application Licensing Platforms Included FPGA Advantage for VHDL, Verilog, Text, Graphics, FPGA with ASIC Nodelocked Windows: 98, NT, 2000 HDL Author, Personal HDL Design or mixed-hdl or Pro (both Text option for Level 3 or Floating ModelSim PE, and Graphics) LeonardoSpectrum (Level 2 or 3) FPGA Advantage with VHDL, Verilog, Text, Graphics, FPGA with ASIC Nodelocked Windows: 98, NT, 2000 HDL Designer, Personal Simulation mixed-hdl or Pro (both Text option for Level 3 or Floating ModelSim PE, and Graphics) LeonardoSpectrum (Level 2 or 3) FPGA Advantage for VHDL, Verilog, Text, Graphics, FPGA with ASIC Floating Windows: 98, NT, 2000 HDL Designer, HDL Design HDL, mixed-hdl, or Pro (both Text option for Level 3 ModelSim SE, or PLUS (separate and Graphics) UNIX: Sun Solaris 2.7/8, LeonardoSpectrum VHDL and Verilog HP-UX 10.20, 11.0 Level 3, licenses) LeonardoInsight

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8 Corporate Headquarters Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR Phone: Sales and Product Information Phone: Silicon Valley Headquarters Mentor Graphics Corporation 1001 Ridder Park Drive San Jose, California USA Phone: Fax: North American Support Center Phone: Europe Headquarters Mentor Graphics Corporation Immeuble le Pasteur 13/15, rue Jeanne Braconnier Meudon La Forêt France Phone: 33 (0) Fax: 33 (0) Pacific Rim Headquarters Mentor Graphics (Taiwan) Room 1603, 16F International Trade Building No. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Phone: Fax: Japan Headquarters Mentor Graphics Japan Co., Ltd. Gotenyama Hills 7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 Japan Phone: Fax: WCI Copyright 2001 Mentor Graphics Corporation. HDL Designer Series, IDL, Interface-Based Design, HDL2Graphics, LeonardoSpectrum, and Time Closer are trademarks and FPGA Advantage and ModelSim are registered trademarks of Mentor Graphics Corporation. All other trademarks mentioned in this document are trademarks of their respective owners.