ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Resources: User Guide Chapter 1: Block RAM Resources 7 Series FPGAs Configurable Logic Block: User Guide Chapter 2: Functional Details: Distributed RAM 2 Types ROM RAM Types Single port Dual port With asynchronous read With synchronous read 3 4 Types specific to Xilinx FPGAs Distributed (MLUT-based) Inferred Block RAM-based (BRAM-based) Instantiated FPGA Distributed Manually Using Vivado 5 1
Location of Distributed RAM SLICEL Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 7 8 Fast Carry Logic Accessing Carry Logic u u Each SliceL and SliceM contains separate logic and routing for the fast generation of sum & carry signals Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters Carry logic is independent of normal logic and routing resources MSB LSB Carry Logic Routing u All major synthesis tools can infer carry logic for arithmetic functions Addition (SUM <= A + B) Subtraction (DIFF <= A - B) Comparators (if A < B then ) Counters (count <= count +1) 9 10 SLICEM ECE 448 FPGA and ASIC Design with VHDL 11 ECE 448 FPGA and ASIC Design with VHDL 12 2
Xilinx Multipurpose LUT (MLUT) Single-port 64 x 1-bit RAM 16-bit 32-bit SR 16 64 x 1 RAM 4-input 64 x 1 ROM LUT (logic) The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 13 14 Single-port 64 x 1-bit RAM Memories Built of Neighboring MLUTs Memories built of 2 MLUTs: Single-port 128 x 1-bit RAM: RAM128x1S Dual-port 64 x 1-bit RAM : RAM64x1D Memories built of 4 MLUTs: Single-port 256 x 1-bit RAM: RAM256x1S Dual-port 128 x 1-bit RAM: RAM128x1D Quad-port 64 x 1-bit RAM: RAM64x1Q Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP (one address for read, one address for write) 15 16 Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S Dual-port 64 x 1 RAM Dual-port 64 x 1-bit RAM : 64x1D Single-port 128 x 1-bit RAM: 128x1S 17 18 3
Location of Block RAMs Logic resources (CLB slices) RAM blocks Multipliers DSP units Logic Logic resources blocks FPGA Block RAM Graphics based on The Design Warrior s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright 2004 Mentor Graphics Corp. (www.mentor.com) 19 20 Block RAM Block RAM Configured as 1 x 36 kbit RAM or 2 x 18 kbit RAMs Simple Dual Port (SDP) = one port for read, one port for write (write_a-read_b, read_a_write_b) True Dual Port (TDP) = both ports can be used for read or write (read_a-read_b, read_a-write_b, write_a-read_b, write_a-write_b) 21 22 Block RAM can have various configurations (port aspect ratios) 0 1 0 2 8k x 2 4k x 4 0 4 16k x 1 8,191 0 2047 4,095 8+1 2k x (8+1) 16,383 0 1023 16+2 1024 x (16+2) 23 24 4
18k Block RAM Port Aspect Ratios 25 26 Block RAM Interface Block RAM Ports 27 28 Cascadable Block RAM Block RAM Waveforms READ_FIRST mode 29 30 5
Block RAM Waveforms WRITE_FIRST mode Block RAM Waveforms NO_CHANGE mode 31 32 Features of Block RAMs Inference vs. Instantiation 33 34 Generic Inferred ROM 35 36 6
Distributed ROM with asynchronous read Distributed ROM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; Entity ROM is generic ( w : integer := 12; -- number of bits per ROM word r : integer := 3); -- 2^r = number of words in ROM port (addr : in std_logic_vector(r-1 downto 0); dout : out std_logic_vector(w-1 downto 0)); end ROM; architecture behavioral of rominfr is type rom_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := ("000011000100", "010011010010", "010011011011", "011011000010", "000011110001", "011111010110", "010011010000", "111110011111"); dout <= ROM_array(to_integer(unsigned(addr))); 37 38 Distributed ROM with asynchronous read architecture behavioral of rominfr is type rom_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); constant ROM_array : rom_type := (X"0C4", X"4D2", X"4DB", X"6C2", X"0F1", X"7D6", X"4D0", X"F9F"); dout <= ROM_array(to_integer(unsigned(addr))); Generic Inferred RAM 39 40 Distributed versus Block RAM Inference Examples: 1. Distributed single-port RAM with asynchronous read 2. Distributed dual-port RAM with asynchronous read 3. Block RAM with synchronous read (no version with asynchronous read!) More excellent RAM examples from XST Coding Guidelines. Distributed single-port RAM with asynchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; 41 42 7
Distributed single-port RAM with asynchronous read architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); process (clk) if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end process; do <= RAM(to_integer(unsigned(a))); Distributed dual-port RAM with asynchronous read library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 6); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(r-1 downto 0); dpra : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); spo : out std_logic_vector(w-1 downto 0); dpo : out std_logic_vector(w-1 downto 0)); end raminfr; 43 44 Distributed dual-port RAM with asynchronous read Block RAM Waveforms READ_FIRST mode architecture syn of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); process (clk) if rising_edge(clk) then if (we = '1') then RAM(to_integer(unsigned(a))) <= di; end process; spo <= RAM(to_integer(unsigned(a))); dpo <= RAM(to_integer(unsigned(dpra))); end syn; 45 46 Block RAM with synchronous read LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; entity raminfr is generic ( w : integer := 32; -- number of bits per RAM word r : integer := 9); -- 2^r = number of words in RAM port (clk : in std_logic; we : in std_logic; en : in std_logic; addr : in std_logic_vector(r-1 downto 0); di : in std_logic_vector(w-1 downto 0); do : out std_logic_vector(w-1 downto 0)); end raminfr; Block RAM with synchronous read Read-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); process (clk) if rising_edge(clk) then if (en = '1') then do <= RAM(to_integer(unsigned(addr))); if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; end process; 47 48 8
Block RAM Waveforms WRITE_FIRST mode Block RAM with synchronous read Write-First Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); process (clk) if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; do <= di; else do <= RAM(to_integer(unsigned(addr))); end process; 49 50 Block RAM Waveforms NO_CHANGE mode Block RAM with synchronous read No-Change Mode - cont'd architecture behavioral of raminfr is type ram_type is array (0 to 2**r-1) of std_logic_vector (w-1 downto 0); signal RAM : ram_type := (others => (others => '0')); process (clk) if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(to_integer(unsigned(addr))) <= di; else do <= RAM(to_integer(unsigned(addr))); end process; 51 52 Criteria for Implementing Inferred RAM in BRAMs FIFOs 53 54 9
FIFO Interface Operation of the Standard FIFO clk rst clk FIFO rst 8 din full dout empty 8 A B C D write read ECE 448 FPGA and ASIC Design with VHDL 55 56 Operation of the First-Word Fall-Through FIFO 57 10