LOW-VOLTAGE 0-BIT BUS ITCH IDT74CBTLV84 FEATURES: 5Ω A/B bi-directional bus switch Isolation under power-off conditions Over-voltage tolerant Latch-up performance exceeds 00mA VCC =.V -.6V, Normal Range ESD > 00 per MIL-STD-88, Method 05; > 0 using machine model (C = 00pF, R = 0) Available in QSOP and TSSOP packages APPLICATIONS:.V High Speed Bus Switching and Bus Isolation DESCRIPTION: The CBTLV84 is a ten bit high-speed bus switch with low on-state resistance of the switch allowing connections to be made with minimal propagation delay. The device is organized as dual 5-bit bus switches with separate outputenable (OE) inputs, to allow use as two 5-bit bus switches or one 0-bit bus switch. When OE is low, the associated 5-bit bus switch is on and A port is connected to B port. When OE is high, the switch is open, and a highimpedance state exists between the two ports. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTIONAL BLOCK DIAGRAM SIMPLIFIED SCHEMATIC, EACH ITCH A B A5 0 B5 OE A B A 4 5 B A5 0 B5 OE OE The IDT logo is a registered trademark of Integrated Device Technology, Inc. DECEMBER 04 04 Integrated Device Technology, Inc. DSC-574/6
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS () Symbol Description Max Unit VCC SupplyVoltage Range 0.5 to +4.6 V OE B A A B B 4 5 6 4 0 9 VCC B5 A5 A4 B4 B VI Input Voltage Range 0.5 to +4.6 V Continuous Channel Current 8 ma IIK Input Clamp Current, VI/O < 0 50 ma TSTG Storage Temperature 65 to +50 C. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. A 7 8 A A4 8 7 A B4 B5 A5 9 6 0 5 4 B B A OE FUNCTION TABLE () Input Inputs/Outputs OE OE B - B5 B - B5 L L A - A5 A - A5 L H A - A5 Z QSOP/ TSSOP TOP VIEW H L Z A - A5 H H Z Z. H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance OPERATING CHARACTERISTICS, TA = 5 C () Symbol Parameter Test Conditions Min. Max. Unit VCC Supply Voltage..6 V High-Level Control Input Voltage VCC =.V to.7v.7 V VCC =.7V to.6v VIL Low-Level Control Input Voltage VCC =.V to.7v 0.7 V VCC =.7V to.6v 0.8 TA Operating Free-Air Temperature 40 85 C. All unused control inputs of the device must be held at VCC or to ensure proper device operation.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Conditions: TA = 40 C to +85 C Symbol Parameter Test Conditions Min. Typ. Max. Unit VIK Control Inputs, Data I/O VCC = V, II = 8mA. V II Control Inputs, Data I/O VCC =.6V, VI = VCC or ± μa IOZ Data I/O VCC =.6V, VO = 0 or.6v, switch disabled 5 μa IOFF VCC = 0, VI or VO = 0 to.6v 50 μa ICC VCC =.6V, IO = 0, VI = VCC or 0 μa ΔICC () Control Inputs VCC =.6V, one input at V, other inputs at VCC or 00 μa CI Control Inputs VI = V or 0 4 pf CIO(OFF) VO = V or 0, OE = VCC 7 pf Max. at VCC =.V VI = 0 IO = 64mA 5 8 Typ. at VCC =.5V IO = 4mA 5 8 RON () VI =.7V IO = 5mA 7 40 Ω VI = 0 IO = 64mA 5 7 VCC = V IO = 4mA 5 7 VI =.4V IO = 5mA 0 5 NOTES:. The increase in supply current is attributable to each current that is at the specified voltage level rather than VCC or.. This is measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B ) terminals. ITCHING CHARACTERISTICS VCC =.5V ± 0.V VCC =.V ± 0.V Symbol Parameter Min. Max. Min. Max. Unit tpd () Propagation Delay 0.5 0.5 ns A to B or B to A ten Output Enable Time 5 4. ns OE to A or B tdis Output Disable Time 5.5 5.5 ns OE to A or B. The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance driven by an ideal voltage source (zero output impedance).
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC () =.V±0.V VCC () =.5V±0.V Unit VLOAD 6 x Vcc V Vcc V.5 Vcc / V VLZ 00 50 mv VHZ 00 50 mv CL 50 0 pf (, ) Pulse Generator VIN RT VCC D.U.T. VOUT CL Test Circuits for All Outputs 500 500 DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES:. Pulse Generator for All Pulses: Rate 0MHz; tf.5ns; tr.5ns.. Pulse Generator for All Pulses: Rate 0MHz; tf ns; tr.5ns. VLOAD Open SAME PHASE INPUT TRANSITION OPPOSITE PHASE INPUT TRANSITION CONTROL INPUT ITCH NORMALLY CLOSED LOW tpzh NORMALLY HIGH tplh tplh Propagation Delay ENABLE tpzl ITCH OPEN VLOAD/ tphl tphl DISABLE tphz tplz Enable and Disable Times VOH VOL VLOAD/ VOL + VLZ VOL VOH VOH -VHZ ITCH POSITION Test tplz/tpzl tphz/tpzh tpd Switch VLOAD Open 4
ORDERING INFORMATION XX CBTLV XXX XX Temp. Range Device Type Package X Blank 8 Tube or Tray Tape and Reel QG PGG Quarter-Size Small Outline Package - Green Thin Shrink Small Outline Package - Green 84 Low-Voltage 0-Bit Bus Switch 74 40 C to +85 C Datasheet Document History /8/04 Pg. 5 Updated the ordering information by removing non RoHS part and by adding Tape and Reel information. CORPORATE HEADQUARTERS for SALES: for Tech Support: 604 Silver Creek Valley Road 800-45-705 or 408-84-800 logichelp@idt.com San Jose, CA 958 fax: 408-84-775 www.idt.com 5