74AC11139 DUAL 2-LINE DECODER/DEMULTIPLEXER

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Todd Marsh
5 years ago
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1 Designed Specifically for High-Speed Memory Decoders and Data Tramission Systems Incorporates Two Enable Inputs to Simplify Cascading and/or Data Reception Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -µm Process -ma Typical Latch-Up Immunity at C Package Optio Include Plastic Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic -mil DIPs (N) D, N, OR PW PACKAGE (TOP VIEW) GND A B G V CC G A B description The circuit is designed to be used in high-performance memory-decoding or data-routing applicatio requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This mea that the effective system delay introduced by the decoder is negligible. The is composed of two individual -line to 4-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applicatio. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit. The is characterized for operation from 4 C to C. FUNCTION TABLE ENABLE SELECT INPUT INPUTS OUTPUTS G A B H X X H H H H L L L L H H H L H L H L H H L L H H H L H L H H H H H L Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Itruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Itruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 logic symbols (alternatives) A B G A B G 4 9 EN X/ A B G A B G 4 9 DMUX G These symbols are in accordance with ANSI/IEEE Std 9-94 and IEC Publication -. logic diagram (positive logic) Enable G Select Inputs A B 4 Data Outputs Enable G A Select B 9 POST OFFICE BOX DALLAS, TEXAS

3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to V Input voltage range, V I (see Note ) V to V CC +. V Output voltage range, V O (see Note ) V to V CC +. V Input clamp current, I IK (V I < or V I > V CC ) ± ma Output clamp current, I OK (V O < or V O > V CC ) ± ma Continuous output current, I O (V O = to V CC ) ± ma Continuous current through V CC or GND ± ma Maximum power dissipation at T A = C (in still air) (see Note ): D package W N package W PW package W Storage temperature range, T stg C to C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.. The maximum package power dissipation is calculated using a junction temperature of C and a board trace length of mils, except for the N package, which has a trace length of zero. recommended operating conditio MIN NOM MAX UNIT VCC Supply voltage. V VCC = V. VIH High-level input voltage VCC = 4. V. V VCC =. V. VCC = V.9 VIL Low-level input voltage VCC = 4. V. V VCC =. V. VI Input voltage VCC V VO Output voltage VCC V VCC = V 4 IOH High-level output current VCC = 4. V 4 ma VCC =. V 4 VCC = V IOL Low-level output current VCC = 4. V 4 ma VCC =. V 4 t/ v Input traition rise or fall rate /V TA Operating free-air temperature 4 C POST OFFICE BOX DALLAS, TEXAS

4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = C MIN TP MAX V.9.9 IOH = µa 4. V V.4.4 MIN MAX UNIT VOH IOH = 4 ma V..4 V IOH = 4 ma 4. V.94.. V IOH = ma. V. V.. IOL = µa 4. V... V.. VOL IOL = ma V..44 V IOL =4mA 4. V..44. V..44 IOL = ma. V. II VI = VCC or GND. V ±. ± µa ICC VI = VCC or GND, IO =. V µa Ci VI = VCC or GND V. pf Not more than one output should be tested at a time, and the duration of the test should not exceed ms. switching characteristics over recommended operating free-air temperature range, V CC =. V ±. V (unless otherwise noted) (see Figure ) PARAMETER FROM TO TA = C (INPUT) (OUTPUT) MIN TP MAX MIN MAX UNIT AorB G switching characteristics over recommended operating free-air temperature range, V CC = V ±. V (unless otherwise noted) (see Figure ) PARAMETER FROM TO TA = C (INPUT) (OUTPUT) MIN TP MAX MIN MAX UNIT AorB G operating characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS TP UNIT Cpd Power dissipation capacitance per gate CL = pf, f = MHz 4 pf 4 POST OFFICE BOX DALLAS, TEXAS

5 PARAMETER MEASUREMENT INFORMATION From Output Under Test Input (see Note B) % VCC % VCC VCC V CL = pf (see Note A) Ω VOH Output % VCC % VCC VOL LOAD CIRCUIT VOLTAGE WAVEFORMS NOTES: A. B. CL includes probe and jig capacitance. Input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = Ω, tr =, tf =. C. The outputs are measured one at a time with one input traition per measurement. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS

6 IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJUR, OR SEVERE PROPERT OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULL AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 99, Texas Itruments Incorporated

74AC11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

74AC11240 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 500-mA Typical Latch-Up Immunity