Class Notes CS400 Part VI Dr.C.N.Zhang Department of Computer Science University of Regina Regina, SK, Canada, S4S 0A2
C. N. Zhang, CS400 83 VI. CENTRAL PROCESSING UNIT 1 Set 1.1 Addressing Modes and Formats Table 1: Basic Addressing Modes. Mode Algorithm Principal Advantage Principal Disadvantage Immediate Operand = A No memory reference Limited operand magnitude Direct EA = A Simple Limited address space Indirect EA = (A) Large address space Multiple memory references Register EA = R No memory reference Limited address space Register indirect EA = (R) Large address space Extra memory reference Displacement EA = A+(R) Flexibility Complexity Stack EA = top of stack No memory reference Limited capability Operand A Memory A Memory A Operand Operand Registers (a) Immediate (b) Direct (c) Indirect (d) Register R Memory R A Memory Implicit Registers Operand Registers Operand Top of Stack Register (e) Register Indirect (f) Displacement (g) Stack Figure 1: Addressing Modes. 1.2 Formats Three-address format: d 3 =(d 1 ) (d 2 ) OP d 1 d 2 d 3 Two-address format: d 1 =(d 1 ) (d 2 ) OP d 1 d 2 One-address format : R =(d) (R) OP d 1 Zero-address format: e.g., stack instructions OP
C. N. Zhang, CS400 84 2 CPU Structure and Functions 2.1 Basic CPU Functions Fetch s: The CPU must read instructions from memory. Interpret s: The instruction must be decoded to determine what action is required. Fetch Data: The execution of an instruction may require reading data from memory or an I/O module. Process Data: The execution of an instruction may require performing some arithmetic or logical operation on data. Write Data: The results of an execution may require writing data to memory or an I/O module. 2.2 CPU Structure Arithmetic and Logic Unit Status Flags Shifter Complementer Arithmetic and Boolean Logic Internal CPU Bus Registers Control Unit Control Paths Figure 2: Internal structure of the CPU. 2.3 Intel 8085 CPU Organization Accumulator: Used as a temporary buer to store input to the ALU. It is also user visible and is addressed in some instructions. Temporary Register: The other ALU input. Flags: These are set as a result of ALU operations. ALU Output: The result of an ALU operation is placed on the bus. Register (IR): Loaded from the MDR via the bus.
C. N. Zhang, CS400 85 Register Array: Discussed presently. Address/Data Buer: This buer connects to multiplexed bus lines. Some of the time, this buer acts as a memory buer register (MDR) to exchange data with the system bus. At other times, it acts as the low-order 8 bits of a memory address register (MAR). This multiplexing allows the 8085 package to have more pins available for control signals to the system bus. Address Buer: Used as the high-order 8 bits of the MAR. Internal CPU Bus Accumulator Temp.Reg. Flags Register ALU Control Unit B reg. C reg. D reg. E reg. H reg. L reg. Stack Pointer Program Counter Address Buffer Address/ Data Buffer Control Bus A 15 - A 8 AD 7 - AD 0 Address Bus Address/Data Bus Figure 3: Internal structure of Intel 8085 CPU. 2.4 Cycle An instruction cycle includes several smaller operation cycles. Each operation cycle consists of one or more bus cycle. The operation cycles are: Fetch cycle (one bus cycle). Indirect cycle (one bus cycle). Execute cycle ( one bus cycles). Interrupt cycle (two bus cycles). DMA cycle (one bus cycle). Fetch Operand Fetch (indirect cycle) Execute Interrupt cycle DMA cycle Figure 4: cycle.
C. N. Zhang, CS400 86 3 Control Unit 3.1 Micro Operation (-op) Each operation in the operation cycle (fetch, indirect, execute, interrupt, and DMA cycle) is further decomposed into a series of smaller operations which are called micro operations (-op). Each -op is a simple task. Each -op can be done in a CPU cycle (t i ). Example: Suppose one bus cycle consists of three CPU cycles. Fetch cycle t 1 : MAR (PC) t 2 : MDR Memory t 3 : PC (PC) + 1 IR (MDR) Indirect cycle t 1 : MAR (IR(Address)) t 2 : MDR Memory t 3 : IR(Address) (MDR(Address)) Execute cycle t 1 : MAR (IR(Address)) t 2 : MDR Memory ; (ADD R1,X) t 3 : R1 (R1) + (MDR) Interrupt cycle (two bus cycles) t 1 : MDR (PC) ; IE 0 t 2 : MAR (SP) SP : stack pointer register t 3 : Memory (MDR) SP (SP) + 1 t 1 : MDR (PSW) t 2 : MAR (SP) t 3 : Memory (MDR) SP (SP) + 1 PC I/O type DMA cycle t 1 : MAR (AR) t 2 : MDR Memory AR (AR)+1 t 3 : DR (MDR) WCR (WCR)-1 3.2 Control Signals Each type of -op is controlled by one control signal (micro control signal). The circuit that produces micro control signals is called micro control unit.
C. N. Zhang, CS400 87 Example: Let A B C D be four 4-bit registers. Suppose there is also one 4-bit adder. One of the operand is selected from one of the registers according to the control signals: C A (select A), C B (select B), C C (select C), or C D (select D). This circuit is shown in the following diagram. Control Signal S 1 S 0 C A (select A) 0 0 C B (select B) 0 1 C C (select C) 1 0 C D (select D) 1 1 C A C B C C C D 4 x 2 Encoder 4-line common bus S 1 S 0 4 x 1 MUX 3 4 x 1 MUX 2 4 x 1 MUX 1 4 x 1 MUX 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 D 2 C 2 B 2 A 2 D 1 C 1 B 1 A 1 D 0 C 0 B 0 A 0 D 2 D 1 D 0 C 2 C 1 C 0 B 2 B 1 B 0 A 2 A 1 A 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Register D Register C Register B Register A Figure 5:. 3.2.1 Diagram of Control Unit Register Flags Control Unit Control Signals within CPU Control Signals from System Bus Clock Control Signals to System Bus Control Bus Figure 6: Logic diagram of control unit.
C. N. Zhang, CS400 88 3.2.2 Inputs of Control Unit Clock: This is how the control unit "keeps time". The control unit causes one microoperation (or a set of simultaneous microoperations) to be performed for each clock pulse. This is sometimes referred to as the processor cycle time, or the clock cycle time. Register: The op code of the current instruction is used to determine which microoperations to perform during the execute cycle. Flags: These are needed by thecontrol unit to determine the status of the CPU and the outcome of the previous ALU operations. For example, for the increment-and-skip-if-zero (ISZ) instruction, the control unit will increment the PC if the zero ag is set. Control Signal from Control Bus: The control bus portion of the system bus provides signals to the control unit, such as interrupt signals and acknowledgments. 3.2.3 Outputs of Control Unit Control Signals within the CPU: These are two types: those that cause data to be moved from one register to another and those that activate specic ALU functions. Control Signals to Control Bus: These are also of two types: control signals to memory and control signals to the I/O modules. Example: C R =Readcontrol signal to system bus. Microoperations Active Control Signals Fetch: t 1 : MAR (PC) C 2 t 2 : MDR Memory C 5, C R PC (PC) + 1 t 3 : IR (MDR) C 4 Indirect: t 1 : MAR (IR(Address)) C 8 t 2 : MDR Memory C 3, C R t 3 : IR(Address) (MDR(Address)) C 4 3.3 Implementation of Micro Control Signals There are two approaches: Logic circuits Microprogram
C. N. Zhang, CS400 89 3.3.1 Logic Circuit Implementation of Control Signals List all micro control signals and number them as: C 1 C 2 :::C m Derive logic expression for each C i according to microoperations Implement C i by a logic circuit Register Decoder I 0 I 1 I k Clock Timing Generator T 1 T 2 Control Unit Flags T n C 0 C 1 Control Signal C m Advantage: fast. Disadvantage: high cost, not exible. Figure 7: Control unit with decoded inputs. 3.3.2 Microprogram Implementation of Control Signals Each micro control signal can be represented by a Boolean variable C i (control variable). When C i = 1, the corresponding op will be executed. Since at any given time one or a set of op can be performed, the control variables can be expressed as a string of 1's and 0's, called a control word. Micro instruction: it consists of a control word, next address, and jump condition. Control Word Jump Conditions Next Address Two formats of micro instructions regarding to the control words: 1. Horizontal micro instruction: each bit of control word represents a micro control signal. Control Word C 1 C 2 C 3 C m Figure 8: Horizontal micro instruction. Advantage: fast Disadvantage: need m bits for the control word.
C. N. Zhang, CS400 90 2. Vertical micro instruction: C i 's are grouped into several control elds. In each eld, only one control signal C i can be set at a time. Additional decoders are required to generate all micro control signals. Control Word Decoder Decoder C 1 C m Figure 9: Vertical micro instruction. Advantage: less number of bits for control word. Disadvantage: slow and need decoders. Two formats of micro instruction regarding to address part: 1. Single address format: there is only one address D in the next address part of the micro instruction. The address of the next micro instruction will be D, if all jump conditions appearing in the jump condition part are satised. Otherwise, the instruction following the current instruction will be executed. Control word Jump condition Next address D 2. Double address format: There are two address elds in the next address part of the micro instruction: D 1 and D 2. The address of the next instruction will be D 2, if all conditions are satised. Otherwise, it will be D 1. Control word Jump condition Next address D 1 Next address D 2 Micro program: a sequence of micro instructions. Micro control memory: a small and high speed memory where micro programs are stored. Organization of micro control memory: each operation cycle (e.g., fetch and execution cycles) is implemented by a subroutine. Jump to Indirect or Execute Jump to Execute Jump to Fetch Jump to Op Code routine Jump to Fetch or Interrupt Jump to Fetch or Interrupt Fetch cycle routine Indirect cycle routine Interrupt cycle routine Execute cycle routine AND Routine ADD Routine Jump to Fetch or Interrupt IOF Routine Figure 10: Organization of control unit.
C. N. Zhang, CS400 91 Example-1: Write micro subroutine for fecth cycle starting at address 00. Recall that fetch cycle is done by the following -ops: t 1 : MAR (PC) C 2 t 2 : MDR Memory C 3 t 3 : PC (PC) + 1 C 1 IR (MDR) C 4 where C i is assigned to one -op. Assume that the microinstruction format is as follows: C 1 C 2 C 16 J Z C I N IR D 1 2 16 17 18 19 20 21 22 23 30 Figure 11: Micro instruction format for example-1. where C 1 ; C 16 are the control word, Z, C, I, N, IR are ags. If J = 1, then those control bits will be checked. Otherwise, those condition bits are ignored. D is the 8-bit address. IR is interrupt request (INTR) ag and I is indirect ag. Subroutine: 00 0100...00000001 01 0010...00000010 02 1001...00000011 Suppose that subroutine for indirect cycle starts at address 03. The corresponding assembly-like program can be written as follows: Address 00 MAR (PC), CAR (CAR) + 1 01 MDR Memory, CAR (CAR) + 1 02 PC (PC) + 1, IR (MDR), CAR (CAR) + 1 03 If I =1 then CAR indirect cycle address else CAR (CAR) + 1 Example-2: Write an assembly-like routine with starting address at 20 for an instruction execution that subtracts the content of register R 2 from the content of register R 1 and places the dierence in register R 3. If (R 1 ) < (R 2 ), then R 4 =(R 4 )+(R 2 ). If (R 1 ) > (R 2 ), then R 4 =(R 4 )+(R 1 ). Suppose all binary numbers are unsigned. Assume there are two as: Flag Z: if the result of adder is 0, then Z = 1. Otherwise, Z =0. Flag C: if there is an end-carry, C = 1. Otherwise, C =0. CAR: em control address register which indicates the address of control memory. The operation to be performed can be summarized as follows: 1 R3 (R1)-(R2). This updates C and Z 2 If (R1) < (R2) (detected by C = 0), then R4 (R4)+(R1) If (R1) > (R2) (detected by C =1andZ = 0), then R4 (R4)+(R2) If (R1) = (R2) (detected by Z = 1), then R4 (R4)+1 3 Output R4 and branch to external address.
C. N. Zhang, CS400 92 Microprogram: Address Microoperations and branch conditions 20 R3 (R1)-(R2), CAR (CAR)+1 21 If (C = 1) then (CAR 23) else (CAR (CAR)+1) 22 R4 (R4)+(R1), CAR 26 23 If (Z =0)then(CAR 25) else (CAR (CAR)+1) 24 R4 (R4)+1, CAR 26 25 R4 (R4)+(R2), CAR (CAR)+1 26 Output (R4), CAR external address 3.3.3 Microprogrammed Control Unit Organization Sequencing logic unit issues a read command to the control memory. According to control address register (CAR), a micro instruction is read into control buer register. Control buer register generates micro control signals and next address information to the sequencing logic unit. Sequencing logic unit loads a new address into CAR. Register Control Unit Decoder ALU Flags Clock Sequencing Logic Control Address Register Control Memory Control Buffer Register Next Address Control Decoder Control Signals within CPU Control Signals to System Bus Figure 12: Microprogrammed control unit.
C. N. Zhang, CS400 93 Microinstruction sequencing: get the next micro instruction from micro control memory. 1. Two address eld: CAR Address Decoder Control Memory CBR Control Address Address 1 2 Flags Branch Logic Address Selection Multiplexer IR 2. Single address eld: Figure 13: Branch control logic, two address elds. Address Decoder Control Memory CBR Control Address +1 CAR Flags Branch Logic Address Selection Multiplexer IR Figure 14: Branch control logic, single address eld. 4 Other Applications of Microprogramming Realization of Computers Emulation Operating System Support Realization of Special Purpose Design High Level Language Support Microdiagnostics User Tailoring