Exercise 3-1. The Program Controller EXERCISE OBJECTIVES

Exercise 3-1 The Program Controller EXERCISE OBJECTIVES Upon completion of this exercise, you will be familiar with the function of the hardware and software features that digital signal processors have evolved to handle program control. DISCUSSION All digital signal processors, and for that matter general-purpose processors, have a specialized unit dedicated to executing the current instruction and determining the next instruction to execute. Within the TMS320C50 DSP ('C50), the unit is known as the Program Controller. DSP Program Controllers have evolved efficient hardware features to rapidly execute instructions. Program controller hardware is said to have low-overhead (zero-overhead). The Program Controller decodes instructions, manages the pipeline, stores the central processing unit (CPU) status, and decodes conditional operations. 3-7

The following software mechanisms are managed by a DSP Program Controller. branch subroutine reset interrupt repeat conditional processing The software mechanisms listed above, though not unique to all digital signal processors, are used for program control. By using these software mechanisms a DSP programmer is in fact, using specialized hardware features that belong to the Program Controller. The specialized hardware in question can be categorized as follows: Program Counter register stack support repeat counters program counter-related hardware status registers The Program Counter register (often abbreviated PC register) holds the program memory address of the next instruction to be fetched and executed by the program controller. The content of the program counter is updated every instruction cycle. Depending on the previous instruction executed, the surrounding hardware (the program counter-related hardware) usually increments the program counter by one. In certain cases, the program controller is loaded with an entirely different program memory address. 3-8

These cases occur when the previous instruction executed was a program control instruction, such as a call, a return from subroutine, or an interrupt service routine (ISR). Digital signal processors use stacks to save and return address and status information during subroutines and interrupt service routines (ISR). A stack can consist of any memory device. Most often DSPs provide at least one of three kinds of stack support: A stack can consist of any memory device. Most often DSPs provide at least one of three kinds of stack support: shadow registers 3-9

A stack can consist of any memory device. Most often DSPs provide at least one of three kinds of stack support: hardware stack software stack Every time that an interrupt is executed an interrupt context save is initiated. The content of key DSP registers are saved to their respective backup registers (shadow registers). The values in the copied registers are still available to the interrupt service routine (ISR) code but after context save they are protected while held in the shadow registers. The shadow registers are copied back to the CPU registers when the return from subroutine instruction is given. Context save and restore is automatic and reduces DSP ISR overhead; The programmer avoids including the save and restore operations as instructions in the ISR code. The hardware stack is used during interrupts and subroutines to save and restore the content of the Program Counter register. The programmer usually does not have control over the hardware stack. The hardware stack is not used except invisibly during subroutine calls, interrupt service routines and repeat instructions. When a subroutine is called, an interrupt occurs or a repeat is executed, the current contents of the Program Counter register (the return address) is automatically saved to the stack (pushed on to the stack). When a return operation occurs, the return address is retrieved from the stack (popped from the stack) and loaded into the Program Counter. The key advantage of a software stack over a hardware stack is that its depth can be configured by the programmer. This can be done by simply reserving an appropriately sized section of memory. Hardware stacks, in contrast, are usually fairly shallow and the programmer must carefully guard against stack overflow (by avoiding nesting of too many interrupts or subroutines). Which of the following types of stacks is used by DSPs during an interrupt context save? a. software stack b. hardware stack c. interrupt service routine d. shadow register DSP algorithms frequently involve the repetitive execution of a small number of instructions. Such operations are required in FIR and IIR filters, FFT and matrix multiplication algorithms (these are different types of signal processing operations). 3-10

To eliminate looping overhead in DSPs, Program Controllers have been designed with circuits capable of repetitively executing a small number of instructions. The operation they perform is often called hardware looping. The following registers in the 'C50 are used by hardware loops. The Program Counter acts as the instruction cache that stores the instruction to be repeated during single-instruction hardware looping. The RePeaT Counter register holds the count on the number of times the instruction held in the instruction cache must be repeated during single-instruction hardware looping. The multiple-instruction hardware looping registers used in the 'C50 (BRCR, PASR, and PAER) are used for control and status of the hardware loop. Hardware loops, as opposed to software loops, lose no time incrementing or decrementing an index. Example: Difference in the overhead required for a software and a hardware loop. B = 16 RPT #16 LOOP: MAC H0, X0 MAC H0, X0 B = B - 1 Branch to LOOP The above examples implement an FIR filter. The one on the left uses a software loop and the one on the right uses a hardware loop (done using the RPT instruction). The hardware loop executes the RPT instruction only once and then automatically repeats 16 times the multiply and accumulate instruction. Hardware looping overhead is reduced compared with software looping overhead. 3-11

The hardware loop, in this example, executes a single-instruction several times. It is a single-instruction hardware loop. During a single-instruction hardware loop, after the repeat (RPT) instruction is executed: The microcode instruction to be repeated is loaded into the instruction cache (PC register), and a counter (RPTC) is loaded with the value of the number of times the instruction is to be repeated. During the loop, the Program Counter acting as the instruction cache supplies to the Program Controller, the instruction to be executed. Many instructions that take two or more cycles to execute will only take one when executed from within a hardware loop that uses an instruction cache. All DSPs use instruction caches (that are 1-word deep) to implement singleinstruction hardware loops, however, not all DSPs use multi-word instruction caches to implement multi-instruction hardware loops. Multi-instruction hardware loops that don't use an instruction cache must re-read the instructions being repeated each time the processor (Program Controller) proceeds through the loop. By not using an instruction cache and needing to re-read repeated instructions, the program bus cannot be freed. This means that instructions that execute more rapidly in single-instruction hardware loops won't in multi-instruction hardware loops without instruction caches. 3-12

Based on your current knowledge of hardware loops which of the following is true? a. Multi-instruction loops are limited by the number of instructions that can be repeated. b. Single-instruction and multi-instruction loops are often limited by the minimum number of times that a loop can be repeated. c. Single-instruction and multi-instruction loops are often limited by the maximum number of times that a loop can be repeated. d. All of the above. Hardware loops have certain limitations associated with them that are not necessarily associated with software loops. & The number of instructions repeated in multi-instruction loops might be limited by a maximum value. & The minimum and the maximum number of times a loop can be repeated for both single- and multi-instruction loops might also be limited. The fallbacks of traditional software approaches to repeated instruction execution, however, are that: & Branch instructions typically require several instruction cycles to execute. The processor must usually use a register to maintain the loop index, which is the count of the number of times the instruction(s) to be repeated must still be executed. & The processor data path must then be used to increment or decrement the index and test to see if the loop condition has been met. To avoid these problems, DSP processors have evolved special hardware control constructs that repeat either a single instruction or a group of instructions a number of times. 3-13

As stated, the primary role of the Program Controller is to determine the next instruction to be executed. Interrupts are used to signal to a processor both external (a push-button is pressed) and internal (a word is received through the serial port) events. All DSPs use interrupts and most use interrupts as their primary means of communicating with peripherals. An interrupt is an external event that causes the processor to stop executing its current program and to branch to a special block of code called an interrupt service routine (ISR). The ISR code, once called, typically deals with the source of the data that signaled the interrupt. E.g., if a word is received through the serial port, an interrupt is signaled. The ISR will execute the necessary code to process the word. Once an interrupt is signaled to the Program Controller, a branch instruction is executed and the Program Counter is loaded with the pma of a special block of code (often called an interrupt vector). Interrupts can be disabled. In fact, this occurs during DSP initialization, ISRs, and single-instruction hardware loops. It is the Program Controller that disables interrupts for the duration of singleinstruction hardware loop execution. A direct consequence of this inability to access an interrupt is that a programmer must carefully consider the maximum interrupt lockout-time that can be accepted. 3-14

Most processors, including DSPs, sample the status of the interrupt lines every instruction cycle. The processor uses status registers to signal interrupts (once sampled) and other information to the Program Controller. From the previous discussion and procedure sections in this manual you have become acquainted with a few of the status and control registers of the TMS320C50 DSP. Though, not all DSPs can be said to have the same number of status and control registers, it is true that all DSPs do contain these types of registers. Many of the registers used by the 'C50 Program Controller and CPU have equivalent counterparts in other DSPs. PROCEDURE Software Program Control In this procedure section, you will assemble a program using individual pieces of pre-programmed source code. * 1. Open the ex3_1.asm file with an ASCII text editor. * 2. Briefly familiarize yourself with the contents of the file. The ex3_1.asm file is an incomplete DSP program source file. It contains pieces of code (mostly subroutines and ISRs) that must be joined together with missing source statements. Once the source file is completed and compiled the DSP circuit will be able to be used as an audio effects generator. 3-15

The memory initialization directives (.ds and.ps) for the audio effects generator have not been set. * 3. Locate within the ex3_1.asm file, the CODE#1 label. Replace the label with the following memory initialization directive: <TAB> <TAB>.mmregs * 4. Locate within the ex3_1.asm file, the CODE#2 label. Replace the label with the following statement: <TAB> <TAB>.ds <TAB> 00300h * 5. Locate within the ex3_1.asm file, the CODE#3 label. Replace the label with the following statement: <TAB> <TAB>.ps <TAB> 080Ah * 6. Locate within the ex3_1.asm file, the CODE#5 label. Replace the label with the following statements: <TAB> <TAB>.ps <TAB> 0FE00h <TAB> <TAB>.entry The above memory initialization directives instruct the assembler to what addresses within the DSP that the program code and data should be stored. * 7. Save the source file to your personal student folder as: ex3_1v2.asm CALL B RET BCND RPT RPTB RETE IDLE The missing statements to be added to the source file consist either of ISR and subroutine labels or of different software program control instructions (such as the ones shown above). A program control instruction has the effect, once executed, of modifying the contents of the Program Counter. 3-16

The assembled program when loaded into the DSP will generate 3 audio effects. This implies that at least three subroutines will be used by the program. & An echo effect & A flanger effect & A voice effect The MAIN program loop may be interrupted by one of four interrupts. & RINT & XINT & INT1# & INT3# * 8. Locate within ex3_1v2.asm the CODE#7 and CODE#8 labels. * 9. Replace the labels by the following statements: CODE#7: --> MAIN: CODE#8: --> <TAB> B <TAB> MAIN These statements instruct the Program Controller to continue executing NOP (No OPeration). This will continue until an interrupt is signaled to the DSP. See HELP Unit 03 shelp2 Note that before a branch (B) instruction can be used, a label must exist to refer to the location of the branch. 3-17

As stated, the effects generator program uses 4 interrupts. Thus, the program Vector Table must contain 4 source statements. Each Vector Table source statement is a branch instruction that directs the Program Controller to execute the respective interrupt service routines. * 10. Locate within ex3_1v2.asm the CODE#4 label. * 11. Within ex3_1v2.asm, replace the CODE#4 label with the following: <TAB>.ps <TAB> 00802h int1: <TAB> B <TAB> SEL_EFFECT <TAB>.ps <TAB> 00806h int3: <TAB> B <TAB> READ_DIP * 12. Locate within ex3_1v2.asm the CODE#9, CODE#14, and CODE#16 labels. These labels respectively correspond to the RECEIVE, SEL_EFFECT, and READ_DIP interrupt service routine (ISR) program start addresses. See HELP Unit 03 shelp13 * 13. Replace each of the ISR CODE labels with its ISR label (RECEIVE:, SEL_EFFECT:, READ_DIP:). * 14. Locate within ex3_1v2.asm the CODE#18, CODE#20, CODE#23, CODE#25, and CODE#27 labels. 3-18

These labels respectively correspond to the ECHO, FLANGER, VOICE, CODECINIT and AIC_2ND subroutine program start addresses. * 15. Replace each of the CODE labels with its subroutine label (ECHO:, FLANGER:, VOICE:, CODECINIT:, AIC_2ND:). E.g.: CODE#23: --> VOICE: To begin executing an interrupt service routine an interrupt must be signaled, from the MAIN code to the DSP. Only then is the corresponding interrupt vector from the Vector Table taken. To reach anyone of the subroutines either a CALL or a B must be made. * 16. Locate within ex3_1v2.asm the CODE#6 label. The labeled program memory address corresponds to where a CODECINIT subroutine CALL instruction should be inserted. * 17. Replace the label with the following source statement: <TAB> CALL <TAB> CODECINIT * 18. Locate within ex3_1v2.asm the CODE#10, CODE#11, CODE#12, and CODE#13 labels. The labels respectively correspond to the program memory addresses where the RECEIVE ISR conditionally branches off to one of the effects subroutines (echo, flanger, or voice). 3-19

* 19. Respectively replace the labels with the following source statements: <TAB> BCND <TAB> ECHO, EQ <TAB> BCND <TAB> FLANGER, EQ <TAB> BCND <TAB> VOICE, EQ <TAB> RETE The last source statement is a return (RETE) from the RECEIVE subroutine instruction. Every ISR and subroutine requires a return to maincode instruction. * 20. Within ex3_1v2.asm replace the CODE#15, CODE#17, CODE#19, CODE#22, and CODE#24 labels with RETE instructions. These labels respectively correspond to the return to main code instructions for the SEL_EFFECT, READ_DIP, ECHO, FLANGER, and VOICE code. * 21. Within ex3_1v2.asm replace the CODE#26 and CODE#32 labels with RET instructions. The RET instruction, as opposed to the RETE instruction, does not reenable interrupts when executed. Interrupts must be disabled during initialization. * 22. Locate within ex3_1v2.asm the CODE#21 label. * 23. Replace the label with the following instruction: <TAB> RPT <TAB> #512 This label is located within the FLANGER subroutine. The DMOV instruction must be executed 513 times (to move the flanger time-delayed samples) this can be done with a single-instruction hardware loop implemented with the RPT instruction * 24. Locate within ex3_1v2.asm the CODE#28, CODE#29, CODE#30, and CODE#31 labels. * 25. Replace the labels with the following instruction: <TAB> IDLE 3-20

These labels are where the AIC_2ND subroutine must pause processing (IDLE) to wait for acknowledgment from the serial port (using the XINT interrupt) that a word has been sent to the CODEC. * 26. Save the ex3_1v2.asm source file. * 27. Assemble the file, from within your student directory. Execute from your student folder the following command at a DOS prompt: c:\lv91027\bin\dsk5a.exe ex3_1v2.asm -l See HELP Unit 03 shelp3 Effects Generator In this procedure section, you will load and use the Effects Generator program. Note: Before using the C5x VDE please make certain the circuit board power source is turned ON, and that the serial connection is present between the host computer and the DIGITAL SIGNAL PROCESSOR circuit block labeled SERIAL PORT. * 28. Make the circuit board connections shown in the figure. These are the connections to be made to properly operate the Audio Effects Generator program. * 29. Open the C5x VDE. 3-21

* 30. Load the ex3_1v2.dsk program into the DSP. This file is located in your student directory. * 31. Execute the RUN command found on the C5x VDE Toolbar. I/O INTERFACE VALUE DISPLAYED AUDIO EFFECTS MODE EFFECT OF PRESSING INT3# - - - 0 Echo Transmits the DIP switch value (millisecond delay between echoes) to the DSP. - - - 1 Flanger Transmits the DIP switch value (degree of flanging) to the DSP. - - - 2 Voice No effect. * 32. Talk into the microphone and familiarize yourself with the Effects Generator program. INT1# push button: Changes between the effects. INT3# push button: Reads the DIP switch. * 33. Halt the DSP program and close the C5x VDE session when finished using the ex3_1v2 program. Interrupt Context Save In this procedure section, you will familiarize yourself with the basic uses of a context save. * 34. Open the C5x VDE and load ex3_1v2.dsk into the DSP. * 35. Create a breakpoint at the program memory address labeled MAIN. * 36. Press the RUN command found on the C5x VDE Toolbar, this will execute the DSP initialization code. 3-22

To demonstrate an interrupt context save we will force a specific interrupt to occur. The TRANSMIT ISR is executed every time that the XINT interrupt is signaled. XINT is signaled when a sample is transmitted from the DSP serial port register(dxr) to the CODEC. * 37. To force the XINT interrupt to occur, enable the XINT interrupt by editing the IMR register to 0x0027. * 38. Edit the ACC to AAAA AAAA h. * 39. Create a breakpoint at the program memory address labeled TRANSMIT. * 40. Execute the RUN command found on the C5x VDE Toolbar. The XINT interrupt vector is taken and the TRANSMIT ISR is begun. At this point, because the ISR has been executed, key DSP registers have been saved to their shadow registers (this process is called context save). * 41. Edit the ACC to BBBB BBBB h. * 42. Using the C5x VDE STEP OVER command, execute the RETE command to exit the ISR and return to the MAIN program loop. 3-23

Note that the content of the ACC register has returned to AAAA AAAAh, the value it had before entering the TRANSMIT ISR. The context save process stored the contents of key CPU registers (including ACC) before entering the subroutine and returned them on exit. * 43. Close the C5x VDE session. CONCLUSION & The primary role of a Program Controller is to determine the next instruction to be executed. & A Program Controller is made up of a program counter register, program counter related hardware, stack support, repeat counters and status registers. & The Program Counter register holds the program memory address of the next instruction to be fetched by the Program Controller and executed. & DSPs use stacks to save and return address and status information during a subroutine or an interrupt service routine (ISR). & Interrupts are used to signal to a processor both external and internal events. & Most DSPs use interrupts as their primary means of communication with peripherals. 3-24

REVIEW QUESTIONS 1. Which of the following software constructs does not require a Program Controller with stack support? a. branch b. subroutine c. repeat d. interrupt 2. Which of the following hardware features is not part of a Program Controller? a. status registers b. hardware stack c. repeat counters d. program bus 3. Which of the following registers holds the program memory address of the next instruction to be fetched and executed by the Program Controller? a. Program Counter register (PC) b. RePeaT Counter register (RPTC) c. The ACCumulator (ACC) d. Status register 1 (ST1) 4. Which of the following types of events are signaled using an interrupt? a. A word is transmitted by the DSP. b. A word transmitted by the CODEC is received by the DSP. c. A push-button is pressed. d. All of the above. 5. What is the process called, where DSPs use stacks to save and return address and status information during a subroutine or an interrupt service routine? a. Call and return. b. Hardware looping. c. Context save. d. Hardware nesting. 3-25