From Concept to Silicon How an idea becomes a part of a new chip at ATI Richard Huddy ATI Research
From Concept to Silicon Creating a new Visual Processing Unit (VPU) is a complex task involving many people and processes at ATI. The major tasks are: Architectural Definition Block Level Specification Logic Design and Synthesis Design Verification Physical Design Driver Development and Debug Silicon Debug Product Release Let s follow how Multisample Antialiasing (MSAA) became a part of the Radeon 9700.
Architectural Definition Determine the Features, Performance and Cost of a new architecture through an iterative process. Set ambitious Feature, Cost (primarily chip area) and Performance goals based on market requirements. Develop an architecture to meet the goals. Evaluate the architecture in detail: Run high level performance and image quality simulations. Revise the architecture to meet goals. Calculate cost based on area estimates from: On chip memory area Datapath prototype area Control logic in previous similar designs Cut features and performance in areas that are lower priority to meet area goals and re-evaluate.
Architectural Definition (MSAA) For MSAA we needed to do the following: Run MSAA algorithmic simulations to evaluate the image quality results. Added per sample gamma correction. Added centre vs. centroid control. Calculate MSAA memory bandwidth requirements and compare it to the available memory bandwidth. Lossless compression was added to reduce memory bandwidth. Evaluate how many samples and which sample placements give good quality images at a reasonable cost. 2, 4, & 6 sample options with programmable sample locations was selected to provide the best results.
Block Level Specification The architecture is broken down into separate blocks and the details of the design of each block are specified. Detailed area and performance estimates are generated and further feature and performance changes are made. For MSAA the following was considered: Which blocks are involved in MSAA and what do they do? The rasterizer must generate the subpixel information and the Z and Color processing blocks must process pixels at the subpixel level. What control information does the hardware need? A register is needed to select the number of subsamples: 1 (no MSAA), 2, 4, or 6 Determine the true cost of MSAA in terms of silicon area, design complexity, and verification effort.
Logic Design and Synthesis The logic is designed in a Hardware Description Language (HDL) and compiled (synthesized) into a gate level netlist. The synthesizer provides a pre-layout area estimate and a pre-layout timing report of the logic paths that do not meet the clock speed objective. The design is reworked until it meets the speed and area objectives. Some features may be cut due to area or schedule considerations. For MSAA: We found that the compression algorithm logic was too complex to meet the clock speed objective. We needed to find ways to break the function into multiple pipeline stages that met timing.
Design Verification Verify that the hardware provides the specified functions at the required performance level. Tests are run on three different versions of the design and the results compared to make sure that everything in the final design works as expected.
Design Verification (Cont.) This is a critical stage of the design process. Bugs in the final silicon are usually due to operations that were not fully covered in the tests or features which could not be properly cross compared. The functional API level tests must cover all of the features of MSAA: 2, 4, or 6 samples All compression states. Resolving the multisample image to a displayable image. These tests drive the functional debug of the RTL code. The API level and game trace performance tests characterize the MSAA performance so that performance problems can be addressed.
Physical Design Convert the gate level netlist into a transistor level silicon design. Place and Route : Place the logic gates and route the connecting wires. Extract the post layout timing results Improve the gate placement, the wire routing and the logical netlist to meet timing and area goals. After all design rule checks are complete release the design database for fabrication. This is Tape Out. Need to place the MSAA logic near the on chip memories and the other logic that it needs to be connected to. Pipelined the compression logic again to improve timing results caused by placement and routing issues.
Driver Development and Debug Write DirectX and OpenGL Drivers to control the operations of the chip. Debug functional issues on the software emulator and crosscheck on the HDL Simulator. Debug functional and performance issues on the Gate level simulation (accelerated by a hardware simulator box). Provide MSAA by setting up the sample select register in the hardware under application or user control.
Silicon Debug The fabricated silicon chip must be: q Tested before packaging q Packaged q Tested after packaging q Assembled into a board Then the board is powered up and tested. Production Drivers are debugged and performance tuned. The chip is tested across frequency and temperature ranges to assure its reliable operation. Any problems in the chip are fixed and a final version is created. No MSAA bugs!!
Product Release Production chip quantities are delivered from the silicon foundry. Chip yield and speed results are tracked in the production silicon. The final chip silicon is provided to board manufacturers and PC vendors for their qualification testing. Boards are provided to the media and to software developers. Product is announced and available for purchase. 9700 MSAA performance and image quality set new standards in the industry.
Questions? Richard Huddy RHuddy@ati.com