Design Space Exploration Using Parameterized Cores

Transcription

1 RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS UNIVERSITY OF WINDSOR Design Space Exploration Using Parameterized Cores Ian D. L. Anderson M.A.Sc. Candidate March 31, 2006 Supervisor: Dr. M. Khalid 1

2 OUTLINE Introduction Designing Systems Using IP Cores Design Space Exploration (DSE) Genetic-based DSE Case Study Results 2

3 Introduction 3

4 Embedded Systems An embedded system: A device that utilizes computational hardware and applicationspecific software to carry out a specific task. Often hidden from the user of the device (i.e. embedded within a larger system) 4

5 Major Components of an Embedded System Digital Hardware: Embedded System Microprocessor or µc Application-specific hardware generally used for accelerating time-critical tasks Embedded software running on the µp or µc Embedded CPU Software running on CPU Applicationspecific hardware Memory & I/O 5

6 The Challenges of Designing Embedded Systems Improvements in IC process tech. enable more complex and intricate designs to be realized Therefore, designing from scratch is too expensive and timeconsuming for many people Traditional or codesign methodology Hardware Design Hardware Synthesis Placement & Routing System Specification Hardware/Software Partitioning HW/SW Interface Design Integration & Testing Final Embedded System Software Development Compiler Assembler/ Linker 6

7 Designing Systems Using IP Cores 7

8 Core-based Design It makes sense for many designers to use and re-use pre-designed and pretested hardware and software components These are generally known as Intellectual Property (IP) Cores Reduce design time at the expense of some flexibility and area/performance penalty 8

9 Three Classes of (Hardware) IP Cores Soft cores: components described in a hardware description language (HDL) Firm cores: gate-level netlist that is ready for technology mapping, placement and routing, etc. Hard cores: pre-placed and pre-routed circuits Increasing Abstraction & Flexibility RT Level HDL Synthesis Logic Level Tech. mapping, placement & routing, etc. Circuit Level Soft Core HDL description Firm Core Logic primitives (gates, FF s, etc.) Hard Core Circuit Layout 9

10 Soft IP Cores Hardware components described in a hardware description language (HDL) such as VHDL, Verilog, etc. Some advantages of soft cores: Higher level of abstraction easier to understand More flexible designers can change the core by editing source code or selecting parameters (more on that later) Platform independent can be synthesized for any IC technology, incl. FPGAs, ASICs, etc. More immune to obsolescence 10

11 Popular Examples of Soft IP Cores Altera Corp. Nios and Nios II processors Customizable embedded RISC microprocessors targeting certain Altera FPGAs Xilinx Inc. MicroBlaze Flexible 32-bit microprocessor for Xilinx FPGA families Tensilica Xtensa Open-source cores: LEON2 and LEON3 by Gaisler Research 11

12 Parameterized Cores In order to increase core flexibility, many IP cores (esp. soft cores) are parameterized Certain aspects of the hardware s architecture can be changed so that the core can be tailored to suit a specific application more closely E.g. Bit-widths, functional unit implementation, etc. Parameters are essentially variables with a finite set of possible values Assigning values to all parameters of a core produces one configuration 12

13 Classification of Core Parameters Static or dynamic parameters: Static Must be set prior to chip fabrication (e.g. HDL generic statements) Dynamic Can be set after chip fabrication provided the chip has proper facilities built-in Extreme example: FPGAs Two or more parameters can share interdependencies with each other: Hard interdependency: requires simultaneous parameter selection for a valid configuration Soft interdependency: value selection should be done simultaneously in order to create an optimal configuration 13

14 Classification of Core Parameters (Cont d) Classification by Function: Parameters affecting: 1. The bit-width of parts of the core Datapath width, width of address bus, etc. 2. How many sub-components are instantiated E.g. # of registers in register file 3. The type or implementation of components being instantiated E.g. Multiplier implementation 4. How components are connected together 5. Some combination of 1, 2, 3 and 4 14

15 Design Space Exploration (DSE) 15

16 What is the Design Space? Design space the set of all possible HW and SW configurations that will achieve the system s required functionality Configurations are evaluated in terms of how well they meet objectives Design space often contains a large number of possibilities that are suboptimal Therefore the design space should be explored to determine the best configuration for the job The Design Space can be pictured As an n-dimensional space, where n is the number of objectives. For example, a 2-objective space: Objective 2 Design Space Objective 1 16

17 DSE and Multi-objective Optimization DSE is essentially a multi-objective optimization problem The designer must balance a set of competing objectives i.e. min. chip area & power while max. performance Often, there is not one single optimal configuration, but rather a set called the Pareto-optimal set Objective 1 Objective 3 Objective 2 17

18 Pareto-Optimality When optimizing several objectives at once, a configuration is Pareto-optimal if you cannot improve on one objective without sacrificing another Example from geometry: optimize the area of three nonoverlapping circles, A, B and C, within the area of the triangle B A C Pareto-optimal B A C Pareto-optimal Vilfredo Pareto A B C NOT Pareto-optimal (Area of C can be increased without reducing A or B) 18

19 Pareto-Optimality (Cont d) If you do not know the relative priority of each objective, then you are left with a set of nondominated solutions No one solution is better than another, unless one knows which objectives have priority (e.g. it may be most important that circle A be larger) Paretooptimal front The Pareto-optimal set lies on the lower boundary of the design space known as the Pareto-optimal front. Objective 2 Design Space Objective 1 19

20 DSE Using Parameterized Cores Many parameterized cores have multiple parameters and each parameter can have numerous possible values This can lead to potentially thousands, millions (or more) of different possible configurations Each parameter can affect the area, performance and power consumption of the core Many configurations are sub-optimal The goal of DSE is to determine the set of combinations of parameter values that constitute the Pareto-optimal set of configurations The best configuration for an application can be chosen from that set 20

21 Automated Approaches to DSE Obviously, exhaustively searching the design space is tedious and a big waste of time when the number of parameters is large Therefore, a lot of research has focused on automating the process One of the most widely known and applied approaches involves using some form of a genetic or evolutionary-based algorithm 21

22 Genetic and Evolutionary Algorithms A class of optimization algorithms that have been applied to a wide array of problems Many variations, but they all have one thing in common: they take their inspiration from the field of biological sciences They attempt to emulate the biological process of natural selection They have found to be good at solving multiobjective optimization problems 22

23 Genetic-based DSE Case Study 23

24 Objectives of Case Study Preliminary study with the following objective: To investigate the feasibility of applying a genetic algorithm-based approach to a parameterized soft IP core with a sizeable design space in order to approximate its Pareto-optimal set of configurations Altera Nios soft-core processor was chosen as the testcase Ultimately this technique will be applied to other parameterized components in order to assist designers in deriving application-specific processing cores Nios is just a convenient test case 24

25 A Bit About the Altera Nios Processor Popular embedded RISC processor targeting Altera FPGAs Flexible; with the parameters shown at right With just the processor, there are a total of 15,696 possible configurations Parameter Datapath width Instruction decoder Register file size WVALID register Instruction cache size Data cache size Integer multiplication Pipeline optimization Support RLC/RRC Support interrupts/traps Support OCI Module Possible Vals. 16 or 32 bit LE s or ROM 128, 256 or 512 Read-only or writable Off, 1, 2, 4, 8 or 16 kb Off, 1, 2, 4, 8 or 16 kb Software, MSTEP, MUL More stalls, Fewer stalls Yes or No Yes or No Yes or No 25

26 The SEAMO Algorithm The Simple Evolutionary Algorithm for Multiobjective Optimization (SEAMO) by C. Valenzuela (2002) was chosen as the exploration algorithm It is population-based it maintains a set or population of configurations rather than just a single solution As the algorithm progresses, it gradually evolves the population until it converges towards the Pareto-optimal set 26

27 How it works Parameters of the core are represented as genes discrete variables (p i ) with a finite set of possible values Configurations are represented as strings of n genes called chromosomes p 1 p 2 p 3 p n Gene Chromosome 27

28 How it works (Cont d) The population is made up of a set of N chromosomes 1 Population p 1 p 2 p n Objectives o 1 o 2 Each chromosome has an objective vector which stores the values of each objective separately 2 3 p 1 p 2 p n p 1 p 2 p n o 1 o 2 o 1 o 2 There can be any number of objectives N p 1 p 2 p n o 1 o 2 28

29 The Algorithm - Initialization Population Objectives Create an initial population of N individuals randomly Evaluate the objective vectors for each chromosome Record the best-sofar values for each objective N p 1 p 2 p n p 1 p 2 p n p 1 p 2 p n p 1 p 2 p n o 1 o 2 o 1 o 2 o 1 o 2 o 1 o 2 Best-so-far: o 1 o 2 29

30 The Algorithm Offspring Creation For each chromosome in the population: Pair with another, randomly selected individual Apply the crossover operator to produce an offspring Mutate the offspring Parent 1 Random cut-point Parent 2 Offspring Offspring Crossover p 1 p 2 p n + p 1 p 2 p n p 1 p 2 p n Mutation p 1 p 2 p n Gene selected at random and Changed to another possible value 30

31 The Algorithm Replacement Strategy Parent chromosomes are replaced by their offspring based on three rules: 1. Parents are replaced only by their own offspring 2. Offspring only replace parents if they are superior ( elitist strategy ) 3. Duplicates in the population are deleted The newly formed offspring is evaluated based on its objectives One of the two parents is replaced by the offspring if the offspring: Improves on one of the best-so-far values Dominates a parent (i.e. is superior in all objectives) If the offspring already exists in the population, then it is deleted 31

32 The Algorithm Iteration After all individuals in the population have had a chance to produce offspring, one generation of the algorithm has passed The algorithm will pass through several generations before the population converges The population size, N, and the number of generations, G, constitute the parameters of the algorithm Also the number of genes in the chromosome, and the number of objectives can be changed to fit different problems 32

33 Evaluation of Configurations Each individual in the population needs to evaluated in terms of its objectives In this case study, objectives are to: Minimize equivalent LE usage on Stratix FPGA Minimize critical path delay 47 different Nios configurations were synthesized; area and delay data were collected from Quartus II reports Using these data, area and delay estimation equations were established using n- dimensional regression techniques 33

34 Results (To be presented at CCECE06) 34

35 Implementation of the Algorithm Testing of objective functions for 20 random test cases: Area estimation: within 7.22% of actual values (on average) Delay estimation: within 7.58% of actual values (on average) Estimation equations were integrated into a C++ implementation of the SEAMO algorithm The algorithm was run for various population sizes to determine suitable values 35

36 Algorithm Convergence Characteristics Average LE Usage Vs. Generation 4000 Average Equivalent LE's Population = 10 Population = 15 Population = 20 Population = 25 Population = 30 Population = 35 Population = 40 Population = 45 Population = Generation Average Delay Vs. Generation 22 Average Delay (ns) Population = 10 Population = 15 Population = 20 Population = 25 Population = 30 Population = 35 Population = 40 Population = 45 Population = Generation 36

37 Results Area Versus Critical Path Delay for Initial and Evolved Population Area (Equivalent LE's) Critical Path Delay (ns) Initial Population After 20 Generations 37

38 Conclusions and Future Work The purpose of this study was to investigate the feasibility of using a genetic algorithm to design embedded systems It is still a work in progress Genetic algorithms may be useful in assisting designers to make good decisions when deriving application-specific components from parameterized cores Current work involves the development of a tool that will utilize a genetic approach to semiautomatically generate application-specific soft processors from parameterized components 38

39 References [1] Altera Corporation, Nios 3.0 CPU datasheet", October 2004, Version 2.2 [2] Altera Corporation Website, February 2006 [3] Altera Corporation, Nios embedded processor 16-bit programmer's reference manual", January 2004, Version 3.1 [4] Altera Corporation, Nios embedded processor 32-bit programmer's reference manual", January 2003, Version 3.1 [5] Altera Corporation, Avalon bus specification reference manual", July 2003, Version

40 References (Cont d) [6] C. L. Valenzuela, A simple evolutionary algorithm for multi-objective optimization (SEAMO)," Proceedings of the 2002 Congress on Evolutionary Computation, 2002, CEC '02, vol. 1, May 2002, pp [7] P. K. Jha and N. D. Dutt, Rapid estimation for parameterized components in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, issue 3, Sept. 1993, pp [8] P. Yiannacouras, The microarchitecture of FPGA-based soft processors," Master's Thesis, University oftoronto, 2005, pp