HW / SW Implementation
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HW Implementation ASIC (Application Specific Integrated Circuit) RTL design always @(posedge clk) if (load) q = d; Logic Synthesis Gate netlist Physical Synthesis i s i1 U U 2 s b U 1 a a 1 U 3 z clk D Q mask GDS 3
NAND Gate A Transistor Level A Layout A Gate Level A Wafer processed 4
SW Implementation C++ / Java Code int i, s=; for(i=; i<1; ++i) s+= i; Compile Assembly Code addi $s1, $, add $s, $, $ addi $t, $, 1... Link with libraries ELF 5
OS Kernel Process Management Multitasking Interrupts Modes Memory Management Virtual Memory Disk access File System Device Drivers 6
Interrupt Asynchronous INT ISR2 ISR2 Hardware Interrupt User Mode Non-user Mode Synchronous Software Interrupt Instruction SWI ISR4 ISR4 INT x8... Software Interrupt User Mode Non-user Mode 7
Interrupt and Parallelism Asynchronous INT ISR2 ISR2 Hardware Interrupt User Mode Non-user Mode Two parallel threads of execution Simulate parallelism Time sharing 8
Timer & Interrupt Timer TRG_IncTick() INT TMR_Init() ISR CheckCallbacks() Hardware Interrupt void main(void) { TMR_Init(); TRG_Init(); EnableInterrupt(); callback(data) } TRG_SetTrigger( ); for ( ; ; ); Setting callback function & data 9
Multi-tasking Time Slice Time Sharing Round Robin Scheduling Context Switching Task A Thread Task B Thread Task C Thread timer tick interrupt A B C A B C 1
GPIO read from port address write to port address D Q write to port direction register D Q 11
HW (ASIC) & SW Implementations HW (ASIC) RTL design SW C++ / Java Code Logic Synthesis Compile Gate netlist Assembly Code GDS Physical Synthesis Parallelism is ensured by spatial allotment in a chip ELF Link with libraries Parallelism is ensured by temporal processing on a processor 12
FPGA Architecture A Logic Block FPGA (Field Programmable Gate Array) A Configurable Interconnection 13
Implementing Boolean Functions Memory Size : 2 3 x 1 x y z F 1 2 3 1 1 1 1 1 1 1 1 A Logic Block 4 5 6 7 1 1 1 1 1 1 1 1 1 address 3bits 1 index inputs output Data 1 bit A Truth Table LUT (Look up table) Combinational Logic 14
Configuring Logic Blocks A Logic Block LUT SRAM cells An 2-bit SRAM cell select 15
Configuring Interconnections An 1-bit SRAM cell An 1-bit SRAM cell 16
HW (FPGA) Implementations HW (FPGA) RTL design Logic Synthesis An 1-bit SRAM cell An 1-bit SRAM cell Gate netlist * LUTs, FF, etc Physical Synthesis Programming File FPGA configuration information An 2-bit SRAM cell select LUT SRAM cells 17
HW (FPGA) & SW Implementations HW (FPGA) RTL design Gate netlist Logic Synthesis SW C++ / Java Code Compile Assembly Code Physical Synthesis Link with libraries Programming File FPGA configuration information ELF 111111... FPGA configuration information 111... Machine Instructions of a processor 18
References [1] http://en.wikipedia.org/ [2] D.M. Harris, S. L. Harris, Digital Design and Computer Architecture