Recommended Protocol s for Stratix IV GX FPGAs AN-577-3.0 Application Note The architecture of the Altera Stratix IV GX FPGA is designed to accommodate the widest range of protocol standards spread over multiple data rates and data rate ranges. This application note helps you implement the protocols shown in Table 1 using specific configurations of Stratix IV GX FPGAs with transceivers that are not shown in the ALTGX MegaWizard Plug-In Manager of Quartus II software version 8.0 and later. Table 1. Protocol s for Stratix IV GX FPGAs Fibre Channel Interlaken SF1-5.1 Protocols Gigabit-capable passive optical network (GPON) Advanced switching interconnect (ASI) Serial data converter (SDC) (JESD204) SerialLite II Serial ATA (SATA) and Serial attached SCSI (SAS) Refer to Recommended to Achieve Fibre Channel Protocol Implementation on page 2 Recommended to Achieve Interlaken Protocol Implementation on page 4 Recommended to Achieve SFI-5.1 Protocol Implementation on page 7 Recommended to Achieve GPON Protocol Implementation on page 9 Recommended to Achieve ASI Protocol Implementation on page 11 Recommended to Achieve SDC (JESD204) Protocol Implementation on page 13 Recommended to Achieve SerialLite II Protocol Implementation on page 15 Recommended to Achieve SATA and SAS Protocols Implementation on page 16 1 The protocol implementations shown in this application note are the recommended implementations. You have the freedom to implement these protocols in any other configurations appropriate to your specific custom implementations according to your system design constraints, requirements, or both. 1 The recommended configurations described in this application note are used by Altera to characterize the respective protocols. f Detailed functional descriptions of all the blocks shown in the flow charts that follow are available in the Architecture for Stratix IV Devices chapter in volume 2 of the Stratix IV Device Handbook. 101 Innovation Drive San Jose, CA 95134 www.altera.com 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. March 2011 Altera Corporation Subscribe
Page 2 Recommended to Achieve Fibre Channel Protocol Implementation Recommended to Achieve Fibre Channel Protocol Implementation The Fibre Channel protocol manages the transfer of information between different entities within a storage area network (SAN) using a point-to-point link. Table 2 shows the four supported Fibre Channel specifications and their data rates. Table 2. Fibre Channel Data Rates for Stratix IV GX Devices Fibre Channel Specification Data Rate (Gbps) FC-1 1.0625 FC-2 2.125 FC-4 4.25 FC-8 8.5 Although dependent on the system requirements and data rate of the application, any one of the recommended configurations shown in Figure 1 can implement the Fibre Channel protocol in Stratix IV GX transceivers. To use the Fibre Channel protocol, you must add the 8B/10B encoder/decoder to the FPGA fabric. Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve Fibre Channel Protocol Implementation Page 3 Figure 1. Recommended s to Implement the Fibre Channel Protocol in a Stratix IV GX FPGA Stratix IV GX s options for Fibre Channel data rates FC-1 and FC-2 Basic options for Fibre Channel data rates FC-1, FC-2, and FC-4 options for Fibre Channel data rate FC-8 Single PMA-PCS - 10-bit Basic Single- 10-bit PMA-PCS Basic - PMA-PCS Basic - PMA-PCS Data Rate (Gbps) FC-1, FC-2 (1) FC-1, FC-2, FC-4 (1) FC-8 (1) Reference Clock 53.125-531.25 @ FC-1 42.5-531.25 @ FC-2 53.125-531.25 @ FC-1 42.5-531.25 @ FC-2 85.0-680.0 @ FC-4 425.0 Channel Bonding Low-Latency PCS Word Aligner (Pattern Length) (Manual, 7-bit, 10-bit) (Manual, 7-bit, 10-bit, ) (Manual, 7-bit, 10-bit, ) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering 10-bit 40-bit 40-bit FPGA FPGA Fabric Fabric Interface Interface Frequency Frequency - 106.25 for FC-1, 212.5 for FC-2 53.125 for FC-1, 106.25 for FC-2 53.125 for FC-1, 106.25 for FC-2, 212.5 for FC-4 26.5625 for FC-1, 53.125 for FC-2, 106.25 for FC-4 212.5 for FC-8 Note for Figure 1: (1) FC-1 = 1.0625 Gbps, FC-2 = 2.125 Gbps, FC-4 = 4.25 Gbps, and FC-8=8.5 Gbps. March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 4 Recommended to Achieve Interlaken Protocol Implementation Recommended to Achieve Interlaken Protocol Implementation The Interlaken protocol is a serial protocol capable of achieving 10 Gbps to 100 Gbps throughput. Stratix IV GX FPGAs support an Interlaken data rate range of 3.125 Gbps to 6.5 Gbps. This application note describes the recommended configuration for 24 Interlaken channels on one side of the device. In this configuration, all 24 transmitter channels are configured in Basic (PMA-Direct) double-width mode (Figure 2). All 24 receiver channels are also configured in Basic (PMA-Direct) double-width mode (Figure 3 on page 6). This configuration requires two ALTGX instantiations: 1. Twenty-four Transmitter-only channels in Basic (PMA-Direct) double-width mode 2. Twenty-four Receiver-only channels in Basic (PMA-Direct) double-width mode Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve Interlaken Protocol Implementation Page 5 Figure 2. Recommended to Implement 24 Transmitter Channels in PMA-Direct Mode for the Interlaken Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic Single PMA Direct PMA-PCS 10-bit Mode Basic (PMA-Direct) - PMA-FPGA Fabric Data Rate (Gbps) 3.125-6.5 Reference Clock 62.5-625.0 @ 3.125 Gbps 130.0-650.0 @ 6.5 Gbps Channel Bonding Up to x24 Low-Latency PCS Word Aligner (Pattern Length) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering FPGA FPGA Fabric- Fabric- 156.25-325 March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 6 Recommended to Achieve Interlaken Protocol Implementation Figure 3. Recommended to Implement 24 Receiver Channels in PMA-Direct Mode for the Interlaken Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic Single PMA Direct PMA-PCS 10-bit Mode Basic (PMA-Direct) PMA-FPGA Fabric Data Rate (Gbps) 3.125-6.5 Reference Clock 62.5-625.0 @ 3.125 Gbps 130.0-650.0 @ 6.5 Gbps Channel Bonding Low-Latency PCS Word Aligner (Pattern Length) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering 156.25-325 Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve SFI-5.1 Protocol Implementation Page 7 Recommended to Achieve SFI-5.1 Protocol Implementation The serializer/deserializer (SERDES) Framer Interface Level 5.1 (SFI-5.1) protocol is a serial protocol intended for 40-Gbps applications. The 40G solution comprises 16 data channels and one de-skew control channel, for a total of 17 channels. Stratix IV GX FPGAs support SFI-5.1 data rates from 2.488 Gbps to 3.125 Gbps. Figure 4 shows the recommended configuration to implement the SFI-5.1 protocol with 17 transceiver channels configured in Basic (PMA-Direct) double-width mode. March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 8 Recommended to Achieve SFI-5.1 Protocol Implementation Figure 4. Recommended to Implement 17 Channels for the SFI-5.1 Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic Single PMA Direct PMA-PCS 10-bit Mode Basic (PMA-Direct) PMA-FPGA Fabric Data Rate (Gbps) ) 2.488-3.125 Reference Clock 49.76-622.0 @ 2.488 Gbps 62.50-625.0 @ 3.125 Gbps Channel Bonding 7 Low-Latency PCS Word Aligner (Pattern Length) ) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering - FPGA FPGA Fabric- Fabric - 155.52-195.3125 Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve GPON Protocol Implementation Page 9 Recommended to Achieve GPON Protocol Implementation The GPON protocol network provides optical fiber cabling and signals to the home and office using a point-to-multipoint scheme. Stratix IV GX FPGAs support GPON data rates of 155.52 Mbps, 622.08 Mbps, 1.24416 Gbps, and 2.48832 Gbps, with a reference clock of 155.52 MHz. The minimum supported data rate of Stratix IV GX FPGAs is 600 Mbps, so a 5x over-sampling factor is used for the GPON data rate of 155.52 Mbps, resulting in a data rate of 777.6 Mbps. Figure 5 shows the recommended configurations for implementing the GPON protocol in Stratix IV GX FPGAs. March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 10 Recommended to Achieve GPON Protocol Implementation Figure 5. Recommended s to Implement the GPON Protocol in a Stratix IV GX FPGA Stratix IV GX s options for GPON data rates 155.52 Mbps, 622.08 Mbps, and 1.24416 Gbps Basic options for GPON data rates 1.24416 Gbps and 2.48832 Gbps Single PMA Direct PMA-PCS 10-bit Basic - PMA-PCS Basic - PMA-PCS Data Rate ( Gbps) 0.7776-1.24416 1.24416-2.48832 Reference Clock 38.88-622.08 @ 777.6 Mbps 31.104-622.08 @ 1.24416 Gbps 31.104-622.08 @ 1.24416 Gbps 49.76-622.08 @ 2.48832 Gbps Channel Bonding Low-Latency - PCS Word Aligner (Pattern Length) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering FPGA FPGA Fabric- Fabric- 97.2, 77.76, 155.52 77.76, 155.52 Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve ASI Protocol Implementation Page 11 Recommended to Achieve ASI Protocol Implementation The ASI protocol is a serial data-transmission protocol that carries an MPEG-2 video stream. Stratix IV GX FPGAs support an ASI data rate of 270 Mbps. The minimum supported data rate of Stratix IV GX FPGAs is 600 Mbps, so a 5x over-sampling factor is used for the ASI data rate of 270 Mbps, resulting in a data rate of 1.35 Gbps. Figure 6 shows the recommended configuration for implementing the ASI protocol in Stratix IV GX FPGAs. March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 12 Recommended to Achieve ASI Protocol Implementation Figure 6. Recommended to Implement the ASI Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic Single PMA Direct PMA-PCS 10-bit Mode Basic Single- 10-bit PMA-PCS Data Rate (Gbps) 1.35 Reference Clock 27.0-675.0 Channel Bonding Low-Latency PCS Word Aligner (Pattern Length) (Bit-slip,10-bit) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering FPGA Interface Interface Frequency Frequency 10-bit 135 Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve SDC (JESD204) Protocol Implementation Page 13 Recommended to Achieve SDC (JESD204) Protocol Implementation The SDC (JESD204) protocol follows JESD204, a JEDEC standard that enables a high-speed serial connection between analog-to-digital converters and logic devices using only a two-wire high-speed serial interface. Stratix IV GX FPGAs support an SDC (JESD204) data rate range of 312.5 Mbps to 3.125 Gbps. The minimum supported data rate of Stratix IV GX FPGAs is 600 Mbps, so a 5x over-sampling factor is used for the SDC (JESD204) data rate of 312.5 Mbps, resulting in a data rate of 1.5625 Gbps. Figure 7 shows the recommended configurations for implementing the SDC protocol in Stratix IV GX FPGAs. March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 14 Recommended to Achieve SDC (JESD204) Protocol Implementation Figure 7. Recommended s to Implement the SDC (JESD204) Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic PMA-PCS option for SDC data rate range of 312.5 Mbps - 2.0 Gbps Single 10-bit option for SDC data rate range of 2.0 Gbps - 3.125 Gbps Basic Single- 10-bit PMA-PCS Basic Single- 10-bit PMA-PCS Data Rate (Gbps) 1.5625-2.0 2.0-3.125 Reference Clock 31.25-625.0 @ 1.5625 Gbps 40.0-500.0 @ 2.0 Gbps 40.0-500.0 @ 2.0 gbps 62.50-625.0 @ 3.125 gbps Channel Bonding Low-Latency PCS Word Aligner (Pattern Length) (Manual) (Manual) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering 156.25-200 100-156.25 Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve SerialLite II Protocol Implementation Page 15 Recommended to Achieve SerialLite II Protocol Implementation The SerialLite II protocol is a point-to-point communication protocol for data transmission over one or more lanes. The data rate of each lane can be between 622 Mbps and 6.375 Gbps. Figure 8 shows the recommended configurations for implementing the SerialLite II protocol in Stratix IV GX FPGAs. Figure 8. Recommended s to Implement the SerialLite II Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic PMA-PCS option for SerialLite II data rate range of 622 Mbps - 2.0 Gbps Single option for SerialLite II data rate range of 2.0 Gbps - 3.75 Gbps 10-bit option for SerialLite II data rate range of 1.0 Gbps - 3.75 Gbps option for SerialLite II data rate range of 3.75 Gbps - 6.375 Gbps Basic Single- 10-bit PMA-PCS Basic Single- 10-bit PMA-PCS Basic - PMA-PCS Basic - PMA-PCS Data Rate (Gbps) 0.622-2.0 2.0-3.75 1.0-3.75 3.75-6.375 Reference Clock 31.1-622.08 @ 622 Mbps 40.0-500.00 @ 2.0 Gbps 40.0-500.0 @ 2.0 Gbps 75.0-600.0 @ 3.75 Gbps 50.0-500.0 @ 1.0 Gbps 75.0-600.0 @ 3.75 Gbps 75.0-600.0 @ 3.75 Gbps 127.5-637.5 @ 6.375 Gbps Channel Bonding Low-Latency PCS Word Aligner (Pattern Length) (Manual, 10-bit) (Manual, 10-bit) (Manual, 10-bit and ) (Manual, 10-bit and ) 8B/10B Encoder /Decoder Rate Match FIFO Byte SerDes Byte Ordering 32-bit FPGA FPGA Fabric- Fabric- 62.208-200 100-187.5 50-187.5 93.75-159.375 March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 16 Recommended to Achieve SATA and SAS Protocols Implementation Recommended to Achieve SATA and SAS Protocols Implementation SATA is a serial interface between the host bus adaptors and the mass storage devices, such as desktop class disk drives used in consumer PCs, workstations, and laptop computing applications. SAS is a serial interface between the host bus adaptors and the mass storage devices, such as enterprise class disk drives used in servers, disk arrays, and datacenter applications. Table 3 lists the serial data rates supported by Altera s Stratix IV GX devices. Table 3. Serial Data Rates for SATA and SAS Protocols in Stratix IV GX Devices Protocol SATA (Gbps) SAS (Gbps) Gen1 1.5 1.5 Gen1.1 3.0 Gen2 3.0 6.0 Gen3 6.0 Figure 9 shows the recommended configurations for implementing the SATA and SAS protocols in Stratix IV GX devices. The two main requirements of SATA and SAS protocols, out-of-band signaling (OOB) and speed negotiation, are easily implemented in Stratix IV GX devices. The OOB signaling required by SATA and SAS protocol s COMINIT, COMWAKE, COMRESET, and COMSAS sequences require the transmitter to be in the electrical idle power save state and the receiver to detect these valid sequence signals on the link. These requirements are easily implemented in Stratix IV GX devices by using the tx_forceelecidle port on the transmitter-to-transmit electrical idles and the rx_signaldetect port on the receiver-to-detect sequence signal levels above a certain threshold level at the input of the Stratix IV GX receiver. You can set the rx_signaldetect threshold using the Quartus II software version 9.1 or later. The speed negotiation of SATA and SAS protocols requires both the host and device to exchange aligns at the fastest data rate they can both support. This requirement is implemented by using the Stratix IV GX device s capability to dynamically reconfigure data rates. Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation
Recommended to Achieve SATA and SAS Protocols Implementation Page 17 Figure 9. Recommended s to Implement the SATA and SAS Protocol in a Stratix IV GX FPGA Stratix IV GX s Basic PMA-PCS option for SATA/SAS data rate of 1.5 Gbps Single 10-bit option for SATA/SAS data rate of 3.0 Gbps option for SATA/SAS data rate of 1.5 Gbps option for SATA/SAS data rate of 3.0 Gbps option for SATA/SAS data rate of 6.0 Gbps Basic Single- 10-bit PMA-PCS Basic Single- 10-bit PMA-PCS Basic - PMA-PCS Basic - PMA-PCS Basic - PMA-PCS Data Rate (Gbps) 1.5 3.0 1.5 3.0 6.0 Reference Clock 30.0-600.0 60.0-600.0 30.0-600.0 60.0-600.0 120.0-600.0 Channel Bonding 1 1 1 1 1 Low-Latency PCS Word Aligner (Pattern Length) (Manual, 10-bit) (Manual, 10-bit) (Manual, 10-bit) (Manual, 10-bit) (Manual, 10-bit) 8B/10B Encoder/Decoder Rate Match FIFO Byte SERDES Byte Ordering 32-bit 32-bit 32-bit Trasnceiver 150 75 150 75 37.5 150 75 150 March 2011 Altera Corporation Recommended Protocol s for Stratix IV GX FPGAs
Page 18 Document Revision History Document Revision History Table 4. Document Revision History Table 4 lists the revision history for this application note. Date Version Changes March 2011 3.0 Updated the Recommended to Achieve Interlaken Protocol Implementation, Recommended to Achieve GPON Protocol Implementation, and Recommended to Achieve SATA and SAS Protocols Implementation sections. Updated Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, and Figure 9. Updated Table 2. Added Table 3. Removed Figure 4. Converted to the new template. Minor text edits. December 2009 2.0 Added Recommended to Achieve SATA and SAS Protocols Implementation on page 17. May 2009 1.0 Initial release. Recommended Protocol s for Stratix IV GX FPGAs March 2011 Altera Corporation