Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University
Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register etc.
Registers
Registers with Parallel Loads
Shift Register and Serial Transfer Rotate Register Shift Register Serial Transfer (A B) Input Timing Diagram of Serial Transfer
Shift Register and Serial Transfer (Cont.) Example of Serial Transfer Timing pulse Shift register A Shift register B Serial output of B Initial value After T After T2 After T3 After T4
Universal Shift Register (Behavioral Description) Input and Output Diagram Function Table Clear: Low Reset the register CLK: the signal to synchronize the operations S, S : Mode Control Signal I_par: parallel inputs (4-bit) A_par: parallel outputs (4-bit)
Universal Shift Register (Logic Diagram)
Universal Shift Register (HDL Code) <Behavioral Model> <Structural Model> module Shift_Register_4_beh ( output reg [3: ] A_par, // Register output input [3: ] I_par, // Parallel input input s, s, // Select inputs MSB_in, LSB_in, // Serial inputs CLK, Clear // Clock and Clear ); always @ (posedge CLK, negedge Clear) if (~Clear) A_par <= 4'b; else case ({s, s}) 2'b: A_par <= A_par; // No change 2'b: A_par <= {MSB_in, A_par[3: ]}; // Shift right 2'b: A_par <= {A_par[2: ], LSB_in}; // Shift left 2'b: A_par <= I_par; // Parallel load of input endcase endmodule module Shift_Register_4_str ( output [3: ] A_par, // Parallel output input [3: ] I_par, // Parallel input input s, s, // Mode select input MSB_in, LSB_in, CLK, Clear ); // bus for mode control wire [:] select = {s, s}; // Instantiate the four stages stage ST (A_par[], A_par[], LSB_in, I_par[], A_par[], select, CLK, Clear); stage ST (A_par[], A_par[2], A_par[], I_par[],A_par[], select, CLK, Clear); stage ST2 (A_par[2], A_par[3], A_par[], I_par[2], A_par[2], select, CLK, Clear); stage ST3 (A_par[3], MSB_in, A_par[2], I_par[3], A_par[3], select, CLK, Clear); endmodule module stage (i, i, i2, i3, Q, select, CLK, Clr); input i, i, i2, i3; // data from parallel input output Q; input [: ] select; // stage mode control bus input CLK, Clr; // Clock, Clear for flip-flops wire mux_out; Mux_4_x_ M (mux_out, i, i, i2, i3, select); D_flip_flop M (Q, mux_out, CLK, Clr); endmodule
Adders + Adds two N-bit binary numbers 2-bit adder: adds two 2-bit numbers, outputs 3-bit result e.g., + = ( + 3 = 4) + Can we design using combinational design process? s s c b b a Inputs Outputs a
Why Different Design for Adders?
Adders + Adds two N-bit binary numbers 2-bit adder: adds two 2-bit numbers, outputs 3-bit result e.g., + = ( + 3 = 4) + Can we design using combinational design process? s s c b b a Inputs Outputs a
Ripple-Carry Adder + Using half-adder and full-adders, we can build adder that adds like we would by hand + Called a Ripple-Carry adder 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit output 5-bit output can be considered 4-bit sum plus -bit carry out Can easily build any size adder a3 b3 a2 b2 a b a b a b FA co ci s a b FA co ci s a b FA co ci s a b HA co s a3 a2 a a b3 b2 b b 4-bit adder co s3 s2 s s co s3 s2 s (a) s (b)
Ripple-Carry Adder with C in + Using full-adder instead of half-adder for first bit, we can include a carry in bit in the addition Useful later when we connect smaller adders to form bigger adders a3 b3 a2 b2 a b a b ci a b ci a b ci a b ci a b ci a3 a2 a a b3 b2 b b FA FA FA FA 4-bit adder ci co s co s co s co s co s3 s2 s s co s3 s2 s (a) s (b)
Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B Delete = A B Can also derive expressions for S and C o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = A + B
Carry-Bypass Adder C i, P G P G P 2 G 2 P 3 G 3 C o, C o, C o,2 FA FA FA FA C o,3 Also called Carry-Skip P G P G P 2 G 2 P 3 G 3 BP=P o P P 2 P 3 C i, C o, C o, C o,2 FA FA FA FA Multiplexer C o,3 Idea: If (P and P and P2 and P3 = ) then C o3 = C, else kill or generate.
Carry-Select Adder Setup P,G "" "" Carry Propagation "" "" Carry Propagation C o,k- Multiplexer C o,k+3 Sum Generation Carry Vector
Carry Select Adder: Critical Path Bit 3 Bit 4 7 Bit 8 Bit 2 5 Setup Setup Setup Setup -Carry -Carry -Carry -Carry -Carry -Carry -Carry -Carry Multiplexer Multiplexer Multiplexer Multiplexer C i, C o,3 C o,7 C o, C o,5 Sum Generation Sum Generation Sum Generation Sum Generation S 3 S 4 7 S 8 S 2 5
Square Root Carry Select Bit - Bit 2-4 Bit 5-8 Bit 9-3 Bit 4-9 Setup Setup Setup Setup () "" "" Carry "" "" Carry "" "" Carry "" "" Carry () "" "" Carry "" "" Carry "" "" Carry "" "" Carry (3) (3) (4) (5) (6) (4) (5) (6) (7) Multiplexer Multiplexer Multiplexer Multiplexer C i, Sum Generation Sum Generation Sum Generation Sum Generation S - S 2-4 S 5-8 S 9-3 (7) Mux (8) Sum S 4-9 (9)
Serial Adder Using a D F-F
Signed Binary Numbers + Ex) The number 9 represented in binary with eight bit +9 : -9 : (signed-magnitude representation) (signed- s-complement representation) (signed-2 s-complement representation)
Subtraction + Arithmetic Addition - signed-magnitude system follows the rules of ordinary arithmetic. - signed-complement system requires only addition. +6-6 +3 +3 +9 +7 +6-6 -3-3 -7-9 + Arithmetic Subtraction (±A)-(+B) = (±A)+(-B) (±A)-(-B) = (±A)+(+B)
Subtractor Built with an Adder + Using two s complement A B = A + (-B) A B = A + (two s complement of B) N-bit = A + invert_bits(b) + + So build subtractor using adder by inverting B s bits, and setting carry in to A Adder S B cin
Adder/Subtractor + Adder/Subtractor: control input determines whether add or subtract Can use 2x mux sub input passes either B or inverted B Alternatively, can use XOR gates if sub input is, B s bits pass through; if sub input is, XOR inverts B s bits A N-bit 2x A B Adder cin S B N-bit sub b7 b6 adder s B inputs sub
Counter: Ripple Counter LSB MSB Ripple Counter: Clock pulses are applied to the input stage
`timescale ns / ps // time unit = ns, time precision = ps HDL for Ripple Counter <Design Module> module Ripple_Counter_4bit (A3,A2,A,A, Count, Reset); output A3, A2, A, A; input Count, Reset; //Instantiate complementing flip-flop Comp_D_flip_flop F (A, Count, Reset); Comp_D_flip_flop F (A, A, Reset); Comp_D_flip_flop F2 (A2, A, Reset); Comp_D_flip_flop F3 (A3, A2, Reset); Endmodule //Complementing flip-flop with delay //Input to D flip-flop = Q' module Comp_D_flip_flop (Q, CLK, Reset); output Q; input CLK, Reset; reg Q; always @ (negedge CLK, posedge Reset) if (Reset) Q <= 'b; else Q <= #2 ~Q; endmodule //Stimulus for testing ripple counter module testcounter; reg Count; reg Reset; wire A,A,A2,A3; //Instantiate ripple counter Ripple_Counter_4bit M (A3, A2, A, A, Count, Reset); always #5 Count = ~Count; initial begin Count = 'b; Reset = 'b; #4 Reset = 'b; end initial #2 $finish; endmodule <Test Module>
Logic Simulation Results for the previous HDL Code
Counter: BCD Ripple Counter State Diagram 3-decimal BCD counter BCD ripple counter
HDL for Synchronous Counter <Binary Counter> <Up-Down Binary Counter> module Binary_Counter_4_bit ( output reg [3:] A_count, input Count, // Active high to count CLK, // Positive edge sensitive Clear // Active low ); always @ (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b; else if (Count) A_count <= A_count + 'b; else A_count <= A_count; // redundant statement endmodule module Binary_Counter_4_bit ( output reg [3:] A_count, input Up, // Active high Down, // Active high CLK, // Positive edge sensitive Clear // Active low ); always @ (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b; else if (Up == b) A_count <= A_count + 'b; else if (Down == b) A_count <= A_count - 'b; else A_count <= A_count; // redundant statement endmodule
Synchronous Counter : Binary Counter with Parallel Load Input and Output Diagram Function Table Logic Diagram
HDL Code : Binary Counter with Parallel Load module Binary_Counter_4_Par_Load ( output reg [3:] A_count, // Data output output C_out, // Output carry input [3:] Data_in, // Data input input Count, // Active high to count Load, // Active high to load CLK, // Positive edge sensitive Clear // Active low ); assign C_out = Count & (~Load) & (A_count == 4'b); always @ (posedge CLK, negedge Clear) if (~Clear) A_count <= 4'b; else if (Load) A_count <= Data_in; else if (Count) A_count <= A_count + 'b; else A_count <= A_count; // redundant statement endmodule