Joural of Iformatio Systems ad Telecommuicatio, Vol. 2, No. 3, July-September 2014 173 Ehacig Efficiecy of Software Fault Tolerace Techiques i Satellite Motio System Hoda Baki Departmet of Electrical ad Computer Egieerig, Uiversity of Kasha, Isfaha, Ira baki@grad.kashau.ac.ir Seyed Morteza Babamir Departmet of Electrical ad Computer Egieerig, Uiversity of Kasha, Isfaha, Ira babamir@kashau.ac.ir Azam Farokh Departmet of Electrical ad Computer Egieerig, Uiversity of Kasha, Isfaha, Ira farokh@grad.kashau.ac.ir Mohammad Mehdi Morovati* Departmet of Electrical ad Computer Egieerig, Uiversity of Kasha, Isfaha, Ira morovati@grad.kashau.ac.ir Received: 02/Oct/2012 Revised: 07/Ju/2014 Accepted: 02/Aug/2014 Abstract This research shows the ifluece of usig multi-core architecture to reduce the executio time ad thus icrease performace of some software fault tolerace techiques. Accordig to superiority of N-versio Programmig ad Cosesus Recovery Block techiques i compariso with other software fault tolerace techiques, implemetatios were performed based o these two methods. Fially, the compariso betwee the two methods listed above showed that the Cosesus Recovery Block is more reliable. Therefore, i order to improve the performace of this techique, we propose a techique amed Improved Cosesus Recovery Block techique. I this research, satellite motio system which kow as a scietific computig system is cosider as a base for our experimets. Because of existig ay error i calculatio of system may result i defeat i system totally, it should t cotais ay error. Also the executio time of system must be acceptable. I our proposed techique, ot oly performace is higher tha the performace of cosesus recovery block techique, but also the reliability of our proposed techique is equal to the reliability of cosesus recovery block techique. The improvemet of performace is based o multi-core architecture where each versio of software key uits is executed by oe core. As a result, by parallel executio of versios, executio time is reduced ad performace is improved. Keywords: Software Fault Tolerace; Multi-core; Parallel Executio; Cosesus Recovery Block; N-versio Programig; Acceptace Test. 1. Itroductio Nowadays the ifluece of software o differet domais such as ecoomics, medicie, aerospace ad so o is quite sesible. Oe of the mai requiremets of these systems is safety ad reliability of software. Accordig to the importace of software reliability, demad for usig fault tolerace techiques i software developmet have icreased sigificatly. Desig diversity is oe of the fault tolerace methods which eeds to ru multiple versios of the program [1]. software fault tolerace techiques icrease software reliability, o the other had by icreasig umber of versios of the program, executio time icreases at the same time ad this will reduce the performace. by takig advatages of distributed ad parallel processig systems, the efficiecy is icreased ad thus the cost of usig these systems will be acceptable. Usig the multi-core architecture is a good idea for takig advatage of parallel processig. Based o the idea of software fault tolerace, for some software key uits i a system, N versios ca be developed separately with similar fuctioality [2]. The purpose of desig diversity is costructig idepedet modules as may as possible ad miimizig occurrece of idetical errors i these modules [3]. All versios are executed with idetical iitial coditios ad iputs. Output of all versios is give to a decisio module ad the decisio module selects a uique result as a correct output. The paper cotiues as follow: sectio 2 itroduces N-versio programmig ad recovery block ad their derivative techiques. Sectio 3, itroduces satellite motio system as a case study. Sectio 4, discusses the usage of multi-core architecture i fault tolerace techiques. Implemetatio results are reviewed i Sectio 5.the proposed method is preseted i Sectio 6 ad fially i Sectio 7 coclusios are discussed. 2. Software Fault-Tolerace Techiques I this sectio some fault tolerace techiques are itroduced. * Correspodig Author
174 Baki, Babamir, Farokh & Morovati, Ehacig Efficiecy of Software Fault Tolerace Techiques i Satellite Motio System 2.1 N-versio programig techique Usig differet algorithms ad desigs, Most program fuctios ca be performed i various ways. A program versio deotig a separate implemetatio of a program fuctio is called a variat. Each variat has a varyig degree of efficiecy i terms of memory maagemet ad utilizatio, executio time, reliability, ad other criteria. N-versio programmig (NVP) techique is oe of the mai techiques of software fault tolerace. I this techique, N differet versios of a module are implemeted ad executed cocurretly (simultaeously). The the results will be preseted to a decisio module ad this module selects the correct result [3]. The decisio module examies the results ad selects the best oe if exists. There are other available alterative decisio mechaisms. For example oe decisio mechaisms is majority voter. The NVP algorithm techique is show i Fig. 1. Fig. 1. N-versio programmig techique algorithm Other augmetatios, ehacemets, ad combiatios have bee made to the NVP techiques. These are typically give a etirely ew ame rather tha beig called a extesio to the NVP techique. Some of these techiques are described i the followig. 2.2 N-versio programig-tie broker techique I order to improve the performace of NVP techique, N-versio programmig-tie Broker (NVP-TB) techique has bee developed whose strategy is to sychroize the versios. I this techique, assumig that three versios of software key uit are developed, whe the results of two faster versios are produced, it does ot wait for the slowest versio aymore. I other words, whe the two faster versios, complete their executio, their results will be compared ad oe of the results is retured as a correct result if they match, otherwise, it waits for the result of slowest versio ad the the correct result is determied by decisio mechaism [4]. The algorithm of this techique is represeted i Fig. 2. Fig. 2. N-versio programmig-tie broker techique algorithm 2.3 N-versio programig-acceptace test techique To reduce the probability of selectig a icorrect result, Tai ad his colleagues added a acceptace test to the NVP techique. I this techique, after the decisio mechaism selects oe of the results as the correct oe, this result is passed to the acceptace test for checkig its correctess i order to icrease the reliability [4]. The N-versio programig-acceptace test techique is represeted i Fig. 3. Fig. 3. N-versio programmig-acceptace test techique algorithm 2.4 N-versio programig-tie broker- Acceptace test techique Because the two modified NVP techiques are complemetary, N-versio programmig-tie Brokeracceptace test (NVP-TB-AT) techique has bee developed to cocetrate o both reliability ad performace. Actually, this techique is a combiatio of NVP-TB techique ad acceptace test. Acceptace test is used to icrease the reliability which will cause the executio time to icrease ad thus the performace will be reduced. But by usig the Tie-broker techique, reductio of performace is compesated. As a result, ot oly this techique has higher performace tha NVP-AT, but also has reliability equal to NVP-AT[5]. The N-versio programig-tie broker Acceptace test is explaied i Fig. 4. Fig. 4. N-versio programmig-tie broker-acceptace test techique algorithm 2.5 Recovery block techique Recovery block (RcB) techique is oe of the mai techiques of software fault tolerace. This techique works i a way that differet versios are prioritized i order of their importace; the they is ru i order of their prefereces. I other words, RcB icorporates these variats such that the most efficiet module is located first i the series, ad is called the primary alterate or primary try block. Acceptace or rejectio of each versio is idetified by acceptace test module. At first, the overall situatio of system is stored. if o versios ca successfully pass the acceptace test, the system is retured to the saved state ad the the ext module will ru [3]. If o alterates are successful, a error occurs. The algorithm of RcB techique is show i Fig. 5.
Joural of Iformatio Systems ad Telecommuicatio, Vol. 2, No. 3, July-September 2014 175 3. Acceptace Test Fig. 5. Recovery block techique algorithm 2.6 Distributed recovery block techique Distributed recovery block (DRB) techique, is the distributed versio of RcB techique i which several recovery blocks are implemeted i several systems. the oly differece betwee these blocks is the priority of modules [6]. The basic DRB techique cosists of a primary ode ad a shadow ode, each cooperatig with each other ad ruig a RcB scheme. I DRB, the recovery blocks are cocurretly executed o both odes. The iitial primary ode executes the primary algorithm ad the iitial shadow ode executes the alterate alterative oe. First, the techique attempts to esure that the primary algorithm o ode 1 s results passes the AT (i.e., produces a result which passes the test. If this result fails the AT, the the DRB tries the result from the alterate algorithm o ode 2. If either passes the AT, the backward recovery is used to execute the alterate o Node 1 ad the primary o Node 2. The results of these executios are checked to esure the AT. If either of these results passes the AT, the a error occurs. If ay of the results are successful, the result is passed o to the successor computig statio. 2.7 Cosesus recovery block techique The cosesus recovery block (CRB) techique is a combiatio of NVP ad RcB., at first NVP rus ad if it fails to produce the correct result, recovery Block rus ad produces the correct result[3]. The cosesus recovery block techique is represeted i Fig. 6. Fig. 6. Cosesuse Recovery block techique algorithm Whe two or more correct aswers exist for the same problem ad the same iput, we have multiple correct results (MCR). NVP i geeral ad votig-type decisio algorithms i particular, are ot appropriate for situatios i which MCR may occur. It is claimed that the CRB techique reduces the importace of the AT used i the RcB. CRB is Also able to hadle cases i which NVP would ot be appropriate because of MCR. Acceptace Test (AT) is the most basic approach to self-checkig software (Fig. 7), which typically is used with the RcB, CRB ad DRB techiques. The AT is used to verify the acceptace of the systems behavior based o the assertio o the aticipated system state. As show i Fig. 7, a value of TRUE or FALSE is retured. The AT eeds to be simple, effective, ad highly reliable i order to: (1) decrease the chace of additioal desig faults, (2) keep ru-time overhead reasoable, (3) esure detectio of the aticipated faults ad (4) esure that a o-faulty behavior would ot icorrectly be detected. Fig. 7. Acceptace test fuctioality. ATs ca thus be difficult i developmet depedig o their specificatios. Also, the form of a AT depeds o its applicatio. The coverage of a AT is a idicator of its complexity, where a icrease i coverage geerally requires a more complicated implemetatio of the test. Icreasig the complexity leads to icreasig the time of programs executio ad fault maifestatios [3,7]. 4. Satellite Motio System I this sectio the satellite motio system, which is used i scietific computig, is itroduced as a case study. The calculatio of satellite motio is the most critical part of the satellite cotrol system; so, errors i this part lead to failure of etire system. The geodetic satellites have two major missios: (1) positioig i geodesy or (2) to be used as a sesor for measurig the exteral gravity field of the Earth. I order to icrease the reliability of this part, the fault-tolerat software techiques were utilized. Satellite motio equatio is represet i Eq.(1)[8]. The aalytical solutio of this differetial equatio leads to the Kepler orbit [9]. GM r r K 3 r (1) The satellite motio equatio is a secod order vector differetial equatio; therefore it has to be coverted to a first order differetial equatio that is represet i Eq. (2) [8].
176 Baki, Babamir, Farokh & Morovati, Ehacig Efficiecy of Software Fault Tolerace Techiques i Satellite Motio System GM x x 3 K x r GM GM r r K y y K 3 3 y r r GM z z K 3 z r vx x vy y vz z GM vx x K 3 x r GM vy y K 3 y r GM vz z K 3 z r (2) Where, r is the positio vector, GM is the product of gravitatioal costat ad Earth s mass, k is the effects of all the perturbig forces o a satellite. Sice the equatio is a secod order three-dimesioal differetial equatio, it could be solved umerically usig methods such as Ruge-Kutta, Adams-Bashforth ad Adams-Moulto. I this paper, various implemetatios of these methods are used as differet versios of fault-tolerat techiques. Ruge-Kutta, Adams-Bashforth ad Adams-Moulto are the most commo methods for solvig first order differetial equatios umerically. Ruge-Kutta (Eq.(3),(4) ad (5)) solves these equatios i siglephase, while Adams-Bashforth (Eq. (6) ad (7)) ad Adams-Moulto (Eq. (6) ad (8)) solve it i multi-phase. y f ( x, y ) (3) k 1 hf ( x, y ) h k1 k 2 hf ( x, y ) 2 2 h k 2 k 3 hf ( x, y ) 2 2 k 4 hf ( x h, y k 3) (4) h y 1 y ( k 1 2k 2 2k 3 k 4) 6 (5) y ( t ) f ( y, t ) y ( t ) y 0 0 (6) 1 p 1 i ( (1 ), i i 0 y y h f t i h y 1 c c 1 i i 1 i 0 y y h f ( t ih, y ) a (7) (8) 5. Multi-Core Architecture Usage I a sigle-core platform, oly oe thread is ruig at a certai time poit. But I a multi-core platform, there ca be several threads which are ruig o differet cores at the same time. So i the multi-core architecture, threads which are created to ru the program, really ru i parallel o a multi-core platform. Therefore sychroizatio issues ad the cost for commuicatio amog cores are discussed. If the extra cost is quite cosiderable compared to the ormal sigle core executio cost, such applicatios are ot suitable for the multi-core architecture [9]. A software system is composed of a series of software key ad o-key uits (Fig. 8). Each software system icludes critical ad importat parts i which occurrece of error leads to the system failure whose cost caot be compesated. These critical ad importat parts are called software key uits ad other sectios are o-key uits[2]. Fig. 8. o-key software uit ad key software uit Oe way to icrease fault tolerace is usig differet versios ad deploymet of fault tolerace techiques. But sice the developmet of differet versios of the etire system is very costly, several differet versios that have differet implemetatios are developed oly for software key uits. Sice the key uits have several versios which lead to icrease of the executio time, we use multi-core architecture features to reduce time ad ru the versios o differet cores i parallel. This approach reduces executio time ad thus icreases the performace. I compariso with the high cost of the sequetial program, the cost of sychroizatio ad commuicatio betwee the cores is egligible [2]. 6. Implemetatio ad Results of Multi- Core Usage The effect of multi-core architecture o icreasig performace of the NVP techique has bee discussed by Yag et al [10]. I this paper we discuss the effect of multi-core architecture o techiques derived from the NVP, DRB, CRB ad improved cosesus recovery block. I this paper, fault-tolerace techiques have bee used to icrease reliability; so, differet implemetatios of umerical methods for solvig differetial equatios of the satellite motio were used as differet versios i fault tolerace techiques. Accordigly, Ruge-Kutta, Adams-Bashforth ad Adams-Moulto methods are implemeted as differet versios. I other words, i each techique we execute differet versios o sigle ad multi-core architecture ad the
Joural of Iformatio Systems ad Telecommuicatio, Vol. 2, No. 3, July-September 2014 177 compare executio times o the sigle core with the multi-core. Fially, we offer a ew techique to reach a higher performace where the executio times of techiques are sigificatly decreased usig the multicore architecture. As show i Fig. 9, the speedup rate of the NVP techique for dual ad quad core processors is 1.73 ad 2.42 respectively. Because the reliability o this techique is low the NVP-TB-AT Techique is used istead. The speedup rate of this techique is 1.70 ad 2.06 for dual ad quad core processors respectively. The effect of multi-core architecture o performace of the RcB techique is show i Fig. 10. Fig. 9. Executio time of NVP techique ad derived techique The RcB techique executio time o sigle core, dual core ad quad core are 11266, 6413 ad 4718 respectively. I sigle core architecture, all versios are executed sequetially; so the executio time is loger tha other oes. For example, i our implemetatio the executio time of each versio is equal to 1945, 2356 ad 1872 respectively. This meas that the executio time of RcB techique o sigle core is about sum of all these times. I order to apply advatage of parallelism, we ca use distributed versio of this techique amed Distributed Recovery Block (DRB). The DRB techique has 1.76 ad 2.39 speedup rate usig dual ad quad core processors. Show i Fig. 10, the executio time improvemet for quad core architecture is more tha dual core architecture i the case of parallelism. I other words by icreasig the umber of cores, a improvemet of the performace is expected. Fig. 10. Efect of multi-core architecture o performace of recovery block techique 7. Suggested Techique (Improved Cosesus Recovery Block) while usig NVP-TB-AT, if the result of two faster versios were equal, oe of them would be aouced as the correct result ad o acceptace test is performed o the results [5]. So if there is a error i the system that causes the result of two faster versios be similar ad wrog, probability of the overall system failure icreases usig this techique. Thus this techique is less reliable tha RcB techique, because i RcB techique the result goes to the acceptace test module i ay coditios to be retured as a correct result. Also, if a program had several correct aswers, the NVP-TB-AT techique might face failure. If both faster versios produce correct but differet results, the voter waits for the slowest versio ad judges betwee results of two faster versios ad result of slowest versio usig the decisio mechaism. If the lowest versio has a correct but a differet result tha results of faster versios, the voter caot decide ad system will face failure. But, if the RcB techique is used ad the program has several correct results, system does ot fail because the AT is applied to every versio ad so the correct result will be determied. Order of this techique is show by Eq. (9) ad (10). Versios V 1, V 2,, V V Nmber of Versios C Number of Cores Order of Versios f ( V 1), f ( V 2),, f ( V ) F1, F2,, F f ( V ) The Slowest Versio V S C Q ( V ) F1, F2,, F RcB Order O ( Q ( V )) QV ( ) O ( ) if C V C NVP Order QV ( ) O ( ) if C V V DRB Order O ( S f ( V )) CRB Order O (( NVP Order ) ( RcB Order )) ICRB Order O (( NVP Order ) ( CRB Order )) (9) (10) As metioed i Sectio 2, differet versios of RcB techique are executed cosecutively. Accordigly, the RcB techique order is calculated by sum of all versios time order. I the NVP techique, time order is related to the umber of versios ad available cores because of ruig versios simultaeously. I other words, if available cores are more tha the umber of versios, icreasig the umber of cores will be ieffective o decreasig time order. O the other had, while the available cores are equal to or less tha the umber of versios, icreasig the umber of cores leads to decrease of time order.
178 Baki, Babamir, Farokh & Morovati, Ehacig Efficiecy of Software Fault Tolerace Techiques i Satellite Motio System I the DRB techique, the executio steps of versios are computed based o relatioship betwee the umber of versios ad odes (primary ad shadow odes). This meas that the arragemet for ruig versios cosiders that all versios ca be performed by miimum steps. Moreover, accordig to cocurret executio, time order of this techique always depeds o the slowest versio. So, the DRB techique time order is determied by product of the umber of cases i which all versios are executed ad time order of the slowest versio. Sice the CRB techique is a merger of the NVP ad RcB techiques, the proposed techique is a combiatio of NVP ad DRB techiques ad the time order of these two techiques are computed usig sum of costituet techiques time order. O the other had, the performace of the RcB techique is largely depedet o the performace of acceptace test. While i may cases, creatio of the acceptace test module is very difficult, the CRB techique decreases the importace of acceptace test more tha the RcB oe. Also, the NVP techique will ot be able to produce the fial result whe the problem has several correct aswers. So, the RcB ad NVP techiques have drawbacks i some cases which the CRB has resolved by combiig two techiques discussed above. Accordig to superiority of CRB techique over other techiques, we cocetrate o it ad i order to improve its performace, we have proposed a techique which is similar to CRB techique ad called Improved Cosesus Recovery Block. I executio of CRB, first the NVP sectio tries to produce the correct result. If decisio module was able to produce the result, the techique termiates. Otherwise, the secod sectio amely recovery block will execute to produce the correct result. Sice the executio of recovery block is sequetially, the executio time is icreased. The recovery block does ot use multi-core facility ad therefore does ot take advatage of parallel processig. I this paper, i order to take full advatage of multi-core facilities ad reduce the executio time of the CRB techique, we try to use Distributed Recovery Block (DRB) istead of RcB. Fig. 11 shows the proposed algorithm where the first versios are executed simultaeously through NVP techique ad their result is give to a voter. If the voter ca produce a correct result, it returs the result. Otherwise, differet versios are executed through DRB techique. Ifluece of the multi-core architecture o performace of the CRB techique is show i Fig. 12. Differet implemetatios of umerical methods for solvig differetial equatios of satellite motio were used as differet versios which are required i CRB techique. As Fig. 12 shows, the CRB executio time o dual-core ad quad-core architectures is 19106 ad 16044 respectively, while Improved Cosesus Recovery Block executio time o dual-core ad quad-core architectures is 12637 ad 10124 respectively. So Improved CRB decreases total executio time. I other words, the speedup rate of Improved CRB i compariso with CRB for dual-core ad quad-core architectures is 1.51 ad 1.58 respectively. Executio of the NVP sectio is same i CRB ad Improved CRB techiques but the differece is i the recovery block sectio because the CRB executes the recovery block sectio sequetially. T (1) Speed up T ( P) (11) Also, the Improved CRB techique Speed-up for 2, 4 ad 8 Cores cases are represeted i the Table 1, calculated usig Eq.(11)[11] (Prefers to the umber of cores ad T(P) is the executio time usig P cores). Table 1. Speed-up of Improved Cosesus Recovery Block Techique Statuses Speed up 2 Cores 1.78 4 Cores 2.22 8 Cores 2.29 Importat poit of this techique is the close relatio betwee speed-up ad both the umber of versios ad available cores., if the umber of available cores is greater tha the umber of versios, icreasig the umber of cores will be ieffective o Speed-up improvemet. Otherwise, icreasig the umber of cores is effective o speed-up. I the worst case, amely the case i which last versio performs the acceptace test successfully, the executio time will be equal to the total time of ruig all versios. However, i the Improved CRB, the recovery block sectio is executed distributedly ad so its executio time is equal to executio time of the logest versio. Fig. 11. Improved cosesus recovery block techique algorithm Fig. 12. Ifluece of multi-core architecture o performace of cosesus recovery block techique
Joural of Iformatio Systems ad Telecommuicatio, Vol. 2, No. 3, July-September 2014 179 Accordig to Fig. 10, executio time of the DRB techique i quad core architecture is less tha executio time of CRB techique. But sice the CRB does ot have problems of the DRB techique, it is more suitable i may cases. I this paper, we showed that the CRB executio time ca also be decreased. 8. Coclusios Amog differet software fault tolerace techiques the Cosesus Recovery Block (CRB) has more reliability over other oes i some cases ad also it does ot have problems of other techiques. To icrease performace of this techique, we proposed oe techique which is called Improved CRB techique i which the reliability is like the CRB ad because of usig distributio cocepts, it has more performace. Accordig to capability of multi-core architecture for supportig parallel processig, this architecture has bee used to decrease the executio time ad thus icreasig performace of the fault-tolerace techiques. As a result, we showed that the Improved CRB techique is more suitable over other techiques from view of the reliability ad performace properties. Because the satellite motio computatio is the most critical part of the system, i this paper we have used this subsystem as a case study ad software fault tolerace techiques were used to solve the umerical differetial equatio of satellite motio i order to icrease the reliability. To this ed, differet implemetatios of the umerical differetial equatio of the satellite motio methods were employed as differet versios which are required i software fault tolerace techiques. The, to determie the icrease rate of the performace, we compared the executio time for sigle core architecture i the sequetial mode ad for multi-core oe i the cocurret mode i differet fault tolerace techiques. The NVP-TB-AT techique, which has more performace ad reliability over other derived NVP techiques, the executio time i case of sequetial mode at sigle core architecture was 9335 while the executio time i case of the parallel mode at dual-core ad quadcore architecture was 5477 ad 4511 respectively. So, the speedup rate for dual-core ad quad-core architectures is 1.70 ad 2.06 respectively. Moreover, the executio time of recovery block techique o sigle-core, dual-core ad quad-core is 22.04, 16.14 ad 12.14 respectively. Sice high reliability is critical i the satellite motio computatio system, we use the Cosesus Recovery Block techique which has high reliability but its problem is high executio time. This problem was solved by proposig a Improved Cosesus Recovery Block techique. Accordig to our experimets, the best executio time of Improved CRB is at quad-core architecture ad it is equal to 10124, while the executio time of CRB is 16044 at quad core architecture. These two techiques have similar reliability but their performace rate is differet. I other words, Cosesus Recovery Block does ot use distributio ad cocurrecy mechaisms, therefore it caot use advatages of cocurrecy i multi core architecture. The proposed techique has high performace because of takig advatage of distributio mechaism ad usig cocurrecy i multi core architecture. Therefore accordig to the obtaied results, usig Improved Recovery Block techique ad the multi core architecture simultaeously icreases the reliability ad performace i a fault tolerat software. Refereces [1] A. Avizieis ad J. P. J. Kelly, "Fault tolerace by desig diversity- Cocepts ad experimets," IEEE Computer, vol. 17, pp. 67-80, 1984. [2] L. Yag, L. Yu, J. Tag, L. Wag, J. Zhao, ad X. Li, "McC++/Java: Eablig Multi-core Based Moitorig ad Fault Tolerace i C++/Java," i 15th IEEE Iteratioal Coferece o Egieerig of Complex Computer Systems (ICECCS), 2010, pp. 255-256. [3] L. L. Pullum, Software fault tolerace techiques ad implemetatio: Artech House Publishers, 2001. [4] A. T. Tai, J. F. Meyer, ad A. Avizieis, "Performability ehacemet of fault-tolerat software," Reliability, IEEE Trasactios o, vol. 42, pp. 227-237, 1993. [5] A. T. Tai, J. F. Meyer, ad A. Avizieis, Software performability: From cocepts to applicatios: Kluwer Academic Publishers, 1996. [6] K. H. Kim, "The Distributed Recovery Block Scheme," M. R. Lyu(ed.), Software Fault Tolerace, pp. 192-198, 1995. [7] I. Kore ad C. M. Krisha, Fault-tolerat systems: Morga Kaufma, 2007. [8] M. Eshagh ad M. Najafi Alamdari, "Compariso of umerical Itegratio methods i orbit determiatio of low earth orbitig satellites," Joural of The Earth ad Space Physics, vol. 32, pp. 41-57, 2006. [9] S. Akhter ad J. Roberts, Multi-Core Programmig vol. 33: Itel Press, 2006. [10] L. Yag, Z. Cui, ad X. Li, "A case study for fault tolerace orieted programmig i multi-core architecture," i 11th IEEE Iteratioal Coferece o High Performace Computig ad Commuicatios, HPCC '09., 2009, pp. 630-635. [11] B. Parhami, Itroductio to parallel processig: algorithms ad architectures vol. 1: Spriger, 1999.
180 Baki, Babamir, Farokh & Morovati, Ehacig Efficiecy of Software Fault Tolerace Techiques i Satellite Motio System Hoda Baki is M.Sc. studet at Kasha Uiversity i software egieerig. She received B.Sc. degree i software egieerig from Islamic Azad Uiversity Cetral Tehra Brach (IAUCTB) i 2008. Her mai research iterests are high performace computig, distributed systems, quatitative evaluatio of software architecture ad desig based o software architecture styles. Seyed Morteza Babamir received BS degree i Software Egieerig from Ferdowsi Uiversity of Meshhad ad MS ad PhD degrees i Software Egieerig from Tarbiat Modares Uiversity i 2002 ad 2007 respectively. He was a researcher at Ira Aircraft Idustries, Tehra City, Ira, from 1987 to 1993, head of Computer Ceter i Uiversity of Kasha, Kasha, Ira, from 1997 to 1999 ad haed of Computer Egieerig Departmet i Uiversity of Kasha from 2002 to 2005. Sice 2007, he has bee a associate professor of Departmet of Computer Egieerig i Uiversity of Kasha, Kasha, Ira. He authored oe book i Software Testig, four book chapters, fourtee joural papers ad more tha forty iteratioal ad iteral coferece papers (http://ce.kashau.ac.ir/babamir/publicatio.htm). He is maagig director of Soft Computig Joural published by supportig Uiversity of Kasha, Kasha, Ira. He is a member of the ACM. Azam Farokh is M.S. studet at Kasha Uiversity i software egieerig. She received B.S. degree i software egieerig from Arak Uiversity i 2009. Her research iterests are icludig Software Egieerig, high performace computig, Distributed Systems, Fault Tolerat Systems ad software architecture. Her curret research project is Evaluatio of the appropriate style for Adaptive software architecture. Mohammad Mehdi Morovati is M.Sc. studet at Kasha Uiversity i software egieerig. He received B.Sc. degree i software egieerig i 2008 from college of Bahoar. His research iterests iclude the field of Software Egieerig ad Artificial Itelligece ad to date his focus has spaed the areas of Distributed Software Systems, Fault Tolerace Software Systems, High Performace Computig ad Self-adaptive Software Systems.