Parallel Polygon Approximation Algorithm Targeted at Reconfigurable Multi-Ring Hardware

Transcription

1 Parallel Polygo Approximatio Algorithm Targeted at Recofigurable Multi-Rig Hardware M. Arif Wai* ad Hamid R. Arabia** *Califoria State Uiversity Bakersfield, Califoria, USA **Uiversity of Georgia, Georgia, USA Abstract The paper presets a parallel algorithm for polygo approximatio targeted at recofigurable multi-rig hardware. The proposed algorithm grows the edges of polygo approximatio that is based o priciple of mergig. The edge/s are grow simultaeously at poit/s where the miimum mergig error is produced. The mergig process is made faster by carryig it out i two stages: i) Durig first stage it uses templates, geerated durig a off lie process, to carry out fast iitial polygo approximatio, ii) The segmets of the iitial polygo approximatio are further merged durig the secod stage. The simultaeous growig of edges makes the algorithm suitable for a parallel processig hardware. The paper outlies a parallel algorithm for polygo approximatio. It discusses three broadcastig mechaisms for utilizig the multi-rig hardware. The mappig of the polygo approximatio algorithm o the multi-rig topology usig various broadcastig mechaisms is discussed. Idex Terms - Parallel algorithm for polygo approximatio, Local ad global error for polygo approximatio, Recofigurable multi-rig etwork, broadcastig mechaisms for multi-rig etwork. 1 Itroductio Polygo approximatio is a simple techique, but has proved a importat tool for graphics ad image processig applicatios. Its use is ot oly cofied to 2-D image aalysis, as it has also bee used for aalysis of 3-D objects. The polygo approximatio is used i this paper for atural segmetatio of boudaries ad for obtaiig the boudary coditios for aisotropic smoothig. Polygo approximatio is carried out to attai three mai objectives: (i) to smooth out ay irregularities which may be preset i the plaar curves due to either oise or digitisatio effects, (ii) to achieve data reductio ad retai the overall features of the curve, ad (iii) to obtai a simple represetatio of irregular curves. Keepig i view that polygo approximatio forms a part of a pre-processig uit requirig real-time executio i may applicatios, it would be desirable to develop parallel algorithm for polygo approximatio that ca be targeted o a parallel hardware. This paper presets a parallel algorithm for polygo approximatio of plaar curves. The algorithm grows the edges of the polygo approximatio that is based o the priciple of mergig. The edge/s are grow at poit/s where miimum mergig error is produced. This simultaeous growig of edges provides a scope for the parallel implemetatio of the total task, which will make the algorithm faster tha the existig polygo approximatio algorithms. Sectio II provides a review of polygo approximatio algorithms. Proposed parallel polygo approximatio algorithm is described i sectio III. Sectio IV describes parallel hardware for implemetig the parallel polygo approximatio algorithm. Mappig of parallel polygo approximatio algorithm o the proposed parallel hardware is discussed i sectio V. Results ad discussio are preseted i sectio VI. Coclusio is fially preseted i sectio VII. 2. Review of Polygoal Approximatio A umber of polygo approximatio algorithms are described i the literature ad may be broadly classified ito two categories: 2.1 Edge based polygo approximatio. The edge based polygo approximatio algorithms [6,7,8,9,10,11,12,13,14,15,17,18,19,20,23,24] may be divided ito two groups based o the measuremet of error orm: 1) Maximum absolute deviatio error or E orm, ad 2) Absolute area betwee a curve segmet ad its approximatig lie Maximum absolute deviatio error or E orm. The basic priciple of these algorithms is that the maximum absolute deviatio error does ot exceed the allowed error. The logest perpedicular distace betwee a pixel o the give curve ad its correspodig pixel o the approximatig segmet is

2 called the maximum absolute deviatio error or E orm. Differet authors have used E orm i differet ways, which has resulted i algorithms with differet speeds ad slightly differet polygo approximatios for the same curve. Algorithms based o this error orm ca be further divided ito three classes: Iterative method (Split method) [11], Split_ad_merge method [10], ad Sequetial sca methods [13]. Ramer [11] preseted a iterative procedure for the polygo approximatio of plae curves. I this algorithm, the umber of perpedicular distaces computed from the same pixel is usually more tha oe. This depeds o the umber of iteratios required to obtai a segmet that has a maximum absolute deviatio error less tha the allowed error. The procedure eeds two pixels o the curve to start the polygo approximatio process. These are ed pixels for ope curves. For closed curves, the highest left-most ad lowest right-most pixels are take as the startig two pixels. The polygo approximatio of the give curve is obtaied by fidig the poits where maximum absolute deviatio error occurs. If the maximum absolute deviatio error is greater tha the allowed error the the poit is the vertex of the polygo approximatio. The process of obtaiig these poits cotiues util the maximum absolute deviatio error becomes less tha or equal to the allowed error. Pavlidis [10] preseted segmetatio of plaar curves usig split_ad_merge algorithm. The algorithm takes k0 (defied by the user previously) cosecutive pixels at a time to test for colliearity. The colliearity test checks whether the k0 pixels lie withi the allowed error or ot. If the test succeeds the ext k0 pixels are tested. If the test fails the the k0 pixels are split at the mth pixel where the maximum error occurs. The above procedure is repeated util complete polygo approximatio is obtaied. Sklasky ad Gozalez [13] described a techique for fast "sca-alog" computatio of piecewise liear approximatio of digital curves i 2- D. They use a ratchetig procedure to obtai the polygo approximatio. Suzuki et al. [15] address a fast polygo approximatio method for real-time shape recogitio. They do ot perform umerical calculatios to obtai straight lie approximatios. The straight lie approximatio is obtaied by usig polygo edge templates. These templates are geerated by a off-lie process uder a certai defiitio of a straight lie, e.g. 'all succeedig poits must exist i a allowace bad with a defiite width ad a idefiite positio ad orietatio'. The template matchig at each boudary pixel is realized by oly oe poiter referece ad icremet operatio. Therefore, polygo approximatio is carried out at early same speed as boudary trackig. This method has some drawbacks. It limits the legth of polygo edge. Also, it allows three directio scaig oly for template matchig Absolute area betwee a curve segmet ad its approximatig lie. These algorithms are based o the priciple that the area betwee the give curve ad the approximatig lie segmet is ot allowed to go beyod a previously chose value. Wall ad Daielsso [17] have preseted a fast polygo approximatio algorithm which is based o the error orm of area deviatio per uit legth of segmet. It uses a sca-alog techique, where the approximatio depeds o the area deviatio for each lie segmet. The algorithm outputs a ew lie segmet whe the area deviatio per legth uit of the curret segmet exceeds a pre specified value. However, this approach is ot appropriate for real time applicatios. 2.2 Domiat poit based approximatio algorithms. There are two mai steps i these algorithms to obtai the domiat poits. Oe is to compute the measure of relative sigificace (e.g. curvature), ad other is to obtai the regio of support for computig the measure of relative sigificace. To compute curvature oe eeds to defie the regio of support. Teh ad Chi [16] determie the regio of support automatically without usig ay iput parameters. The domiat poits obtaied from these algorithms form the vertices of the polygo approximatio. The domiat poit algorithms have the problem that they detect either less or more poits tha are actually preset. The reaso for this is that curvature is a local property ad is sesitive to local variatios. A small regio of support caot take care of local variatios, ad will therefore produce more domiat poits. A large regio of support will cause loss of accuracy of localizatio, ad will ot be able to obtai domiat poits correspodig to fie features, therefore producig less domiat poits tha are actually preset. Further the algorithm is ot iheretly parallel i ature. 3. Parallel Algorithm We propose a parallel polygo approximatio algorithm that is carried out i two steps: Iitial polygo approximatio, ad Mergig. Iitial polygo approximatio is obtaied by template matchig techique. Template matchig is a very fast techique [15]. The templates are chose such that it maitais both local ad global errors withi the allowed error, ad are geerated durig a off lie process. The origial curve is scaed to match the templates preset i it. Each curve segmet that

3 matches a template is replaced by a straight lie joiig the ed poits of that curve segmet. Note that oly template matchig is required to get the iitial polygo approximatio which takes very little time [15]. The results obtaied from the iitial polygo approximatio are subject to mergig test. The eighborig segmets that result i a error which lies withi allowed error are merged. The above operatios required for polygo approximatio ca be carried out idepedetly i parallel. The algorithm will take less computatioal time whe implemeted o a parallel hardware. A polygo ca be processed simultaeously o various processors to obtai polygo slice approximatios i parallel. The mai steps of the parallel algorithm are give below: Begi Start with a Polygo Divide the polygo ito N polygo slices CoBegi Perform iitial approximatio o the polygo slice 1. Carry out Merge operatio o the polygo slice 1 Perform iitial approximatio o the polygo slice 2. Carry out Merge operatio o the polygo slice 2 Perform iitial approximatio o the polygo slice N. Carry out Merge operatio o the polygo slice N CoEd Collect all slices of the polygo Perform further mergig test ad mergig at ed poits of various polygo slices. Ed. Parallel Algorithm for Polygo Approximatio 4. Recofigurable Multi-rig Hardware This sectio addresses the problem of parallelizig the polygo approximatio, which has bee preseted i earlier sectios. First, we describe the targeted parallel machie architecture; secod, we preset the features of this architecture that are exploited to ehace the performace of the polygo approximatio algorithm. Fially, we show how the proposed algorithm ca be mapped to the proposed parallel system. 4.1 The MultiRig Network. Earlier studies have show [1, 2, 3, 4, 21,22] that a particular etwork of processors, which has bee amed the MultiRig etwork, ca support a wide variety of algorithms ad applicatios. The effectiveess of the MultiRig system is fouded i its recofigurability; the itercoectios betwee processors ca be adjusted to meet phase-specific requiremets. The MultiRig etwork cosists of 2 processors coected i a rig, with the capability to be recofigured, ito R rigs of D processors each, with correspodig elemets of each rig liked, for ay R ad D whose product is 2. The total umber of processors could be ay composite umber, but the use of a power of 2 maximizes the umber of factorizatios. The rig itercoectio etwork has may attractive properties. Oe importat property is that each processor i a rig requires a fixed umber of liks (oly two) irrespective of the size of the etwork; this makes a system with the rig itercoectio etwork truly scalable. Such systems have simpler wirig ad are therefore relatively iexpesive to build. The rig itercoectio etwork does have oe serious drawback - iefficiet iterprocessor commuicatio betwee processors that are ot eighbors. Cosequetly, broadcastig at itercoectio level is a problem. These difficulties have limited the usefuless of the simple rig for a large umber of iterestig problems ad applicatios, but the recofigurable MultiRig does address them. The MultiRig etwork provides a efficiet ad geeral iterprocessor commuicatio ad broadcastig mechaism at the itercoectio level (ulike the simple rig etwork). The MultiRig etwork ca be embedded i the hypercube itercoectio etwork; elsewhere [4] it has bee show that all possible cofiguratios of the MultiRig topology are subsets of the hypercube. Further ivestigatios showed that at ay iterprocessor commuicatio phase, the vast majority of algorithms desiged for ad successfully implemeted o hypercube-based architectures do ot use all the liks provided by the hypercube. It has bee observed that at ay give time durig the executio of most algorithms, the itercoectio subset actually beig utilized (withi the cube) was a cofiguratio of the MultiRig topology. This observatio strogly implies that the MultiRig topology provides the same geerality i practice as the hypercube. The recofiguratio mechaism offered by the MultiRig etwork covers all the umerically balaced cofiguratios withi a system havig ay composite umber of processors. I geeral, a MultiRig havig 2 odes ca be recofigured ito +1 differet cofiguratios. Each of these cofiguratios is referred to as the `umerically balaced rig' or `balaced rig'. s The balaced rigs of a 2 -ode system are 2 rigs s each havig 2 odes where s is a iteger i the rage 0 s. For example, the balaced rigs of a 16- ode system are 16 rigs of 1 ode each, 8 rigs of 2

4 odes each, 4 rigs of 4 odes each, 2 rigs of 8 odes each, ad 1 rig of 16 odes. Cosider a rig of t (t = 2 ) odes where P0 P 1, P 1 P 2,..., P t-1 P 0 (all liks are bidirectioal). This etwork cotais withi it (as its subsets), oe rig of t odes ad t rigs of oe ode each. I order to costruct R rigs of D odes each (R X D = t), two extra liks for each ode, P i, eed to be added to the etwork; as idicated i (1). P i P i P (i+ R) mod t ( 1 P (i+ t-r) mod t As a example, cosider the 16-ode ode rig show i Fig. 1(a) (ote that the techique is applicable to ay composite umber of odes, ot just 16). I order to costruct 2 rigs of 8 odes each (i.e., R=2, t=16, ad D=8), the followig liks eed to be added to the etwork (foud usig the two equatios, Eq. (1), for each ode): P 0 P 2, P 1 P 3, P 2 P 4, P 3 P 5, P 4 P 6, : : P 14 P 0, ad P 15 P 1. This will result the etwork show i Fig. 1(b) which cosists of 2 rigs of 8 odes each. The two rigs withi Fig. 1(b) are formed by: (P 0, P 2, P 4, P 6, P 8, P 10, P 12, P 14 ) ad (P 1, P 3, P 5, P 7, P 9, P 11, P 13, P 15 ). I additio, each ode is coected to the correspodig ode i the other rig (i.e., P 0 P 1, P 2 P 3, ad so o). As aother example, i order to costruct 4 rigs of 4 odes each (i.e., R=4, t=16, ad D=4), the followig liks eed to be added to the origial etwork show i Fig. 1(a) (foud usig the equatios Eq. (1) for each ode): P 0 P 4, P 1 P 5, P 2 P 6, P 3 P 7, P 4 P 8, P 5 P 9, P 6 P 10, P 7 P 11, P 8 P 12, ad so o. This will result the etwork show i Fig. 1(c) which cosists of 4 rigs of 4 odes each. The four rigs withi Fig. 1(c) are formed by: (P 0, P 4, P 8, P 12 ), (P 1, P 5, P 9, P 13 ), (P 2, P 6, P 10, P 14 ), ad (P 3, P 7, P 11, P 15 ). I additio, each ode is coected to the correspodig odes i the other rigs (i.e., P 0 P 1, P 1 P 2, P 2 P 3, P 4 P 5, P 5 P 6, P 6 P 7, P 8 ) P 9, ad so o). All other rig cofiguratios ca be costructed i a similar way. It is importat to ote that the R X D mesh earest-eighbor itercoectio etwork is cotaied withi each cofiguratio. For example, the etwork show i Fig. 1(b) cotais withi it the 2X8 (or 8X2) mesh etwork; similarly, the etwork show i Fig. 1(c) cotais withi it the 4X4 mesh etwork. 4.2 Utilizig The MultiRig Network - Broadcastig Mechaisms. I almost all parallel problems, some form of data broadcastig is required. The MultiRig etwork supports broadcastig at the itercoectio level. Each of the broadcastig operatios performs o the order M o the MultiRig etwork, where M is the legth of the message ad 2 is the umber of odes. This is cosidered to be very efficiet. This broadcast time ca be show optimal amog etworks which are 4-regular, to withi a multiplicative costat that is idepedet of the size of the etwork. Below, three broadcastig mechaisms supported by the MultiRig are described. I the followig descriptios, the ode adjacet to the curret ode i the couterclockwise directio withi a rig is referred to as the ext ode. i) Simple Broadcastig: I simple broadcastig, a block of data i oe ode is to be broadcast to all the other odes. The operatio is performed as follows (assume that A is the data to be broadcast ad iitially there is oe rig of odes; refer to Fig. 1(a)): oe ode seds a copy of A couterclockwise to the ext ode; recofigure the system to yield two rigs (refer to Fig. 1(b)); withi each of the two rigs, two odes each sed a copy of A couterclockwise to the ext ode; recofigure the system to yield four rigs (refer to Fig. 1(c)); withi each of the four rigs, four odes each sed a copy of A to the ext ode; cotiue this process times. After steps each of the 2 odes will have a copy of A. ii) Tile Broadcastig: This broadcastig operatio has may applicatios; it is a particularly useful operatio for parallel patter recogitio (this broadcastig method together with the oe described below have may applicatios i patter recogitio operatios: both i low-level ad high-level operatios required i recogitio problems). I patter recogitio problems, it is ofte ecessary to subdivide the data ito portios of data, called tiles, by horizotal ad/or vertical cuts ad assig each tile to a separate processor for parallel executio. If oe ode has a copy of all the tiles/data i its local memory, the problem is to assig particular tiles/data to particular odes. After performig this assigmet, ode P 0 will cotai tile 0, P 1 will cotai tile 1, ad so o. This operatio is performed as follows (assumig that iitially the tiles are i oe ode i the order: tile 0, tile 1, tile 2, ad so o): sed all those tiles that are umbered with a odd umber

5 (subscript) to the ext ode i the rig (oly the ode with all the data will perform this first task); recofigure the system to yield two rigs, withi each of the two rigs sed all those tiles whose umber (subscript) div 2 (div deotes the iteger divisio operator) is a odd umber to the ext ode i the rig; recofigure the system to yield four rigs, withi each of the four rigs sed all those tiles whose umber (subscript) div 4 is a odd umber to the ext ode i the rig; cotiue this process times. After steps, ode P 0 will cotai tile 0, P 1 will cotai tile 1 ad so o. iii) Gossip Broadcastig: I this type of broadcastig, each ode has a block of data that eeds to be broadcast to all other odes i the system. Therefore, at the ed of this operatio, the data i each ode will be the same as the data i the other odes; i.e., every ode will have a copy of all the blocks of data. This operatio is very similar to the simple broadcastig operatio ad is performed as follows (assumig that iitially there is oe rig of odes): each ode seds a copy of its data to the ext ode; recofigure the system to yield two rigs, withi each of the two rigs each ode seds a copy of its data to the ext ode; recofigure the system to yield four rigs, withi each of the four rigs each ode seds a copy of its data to the ext ode; cotiue this process times. extesio of the gossip broadcast operatio described earlier. vi) The master processor performs further mergig at ed poits of polygo slices. This results i fial polygo approximatio. Steps iii) ad v) ivolve commuicatio. Each of these commuicatios ivolves oly steps o a 2 processor MultiRig etwork. The commuicatio overhead itroduced to parallelize this applicatio is cosidered to be miimal ad is estimated to be about 5% of the overall executio time (excludig the iitial polygo iput to the MultiRig which heavily depeds o the choice of iput devices beig used.) 5. Mappig the polygo approximatio algorithm to the multi-rig topology The recofigurable MultiRig processor etwork ca be effectively used to support the polygo approximatio applicatio described earlier. The MultiRig versio of the algorithm preseted here has bee devised with scalability i mid. The mappig of the parallel polygo approximatio algorithm o the MultiRig topology is described below: i) The polygo is fed ito the MultiRig. Oe processor (loosely amed the "master" processor) ow cotais the polygo data to be approximated. ii) The master processor divides the polygo ito N polygo slices. iii) The master processor the broadcasts the polygo slices to respective multi-rig processors. This is achieved by performig the tile broadcast operatio described earlier. iv) Each multi-rig processor first performs iitial polygo approximatio of its polygo slice. The multirig processors the perform merge operatio o their resultat polygo slices. v) Each multi-rig processor, seds its results to the master processor. This is achieved by a simple Figure MultiRig Topology: a 16-ode example wih three cofiguratios 6. Results ad Discussiom The origial curve for polygoal approximatio was traversed i a clockwise directio ad extreme left poit was take as the startig poit. The results of the polygo approximatio ca be see i Fig 2. Without ay commuicatio, sychroizatio, ad recofiguratio overheads, the executio of the parallel versio of the algorithm preseted i this paper would be p times faster (theoretical optimum) tha its serial versio; where p is the umber of processors i the multiprocessor system. I practice, the mai overhead itroduced i the parallel versio of this applicatio is the commuicatio overhead (we are assumig that the overheads associated with sychroizatio ad recofiguratio are egligible It has bee show that this is a reasoable assumptio for

6 most such applicatios; for VLSI implemetatio of the recofigurable switch, refer to [5].) Figure 2. (a) Origial curve. (b), (c) ad (d) show sequetial sca polygo approximatio at a allowed error of 1,2,3 uits respectively. (e), (f), ad (g) show correspodig results usig Split-ad-Merge algorithm. (h), (i), ad (j) show results of usig Iterative algorithm. (k) ad (l) show the results of the parallel algorithm. Steps iii) ad v) of mappig the parallel algorithm o the multi-rig topology ivolve commuicatio (refer to Sectio IV subsectio C.) The commuicatio time at step iii) is equal to the time it takes for oe processor to sed its whole data to oly oe other processor where there is a direct coectio. The reaso for this is that i order to perform the tile broadcast operatio, first the master processor would sed ½ of the data to its adjacet processor (where there is a direct lik); the system is the recofigured to yield two rigs of odes; withi each ier rig, oly ¼ of the slices are set to the adjacet odes; similarly, at each subsequet commuicatio phase, the size of data to be trasferred is halved (ie, s/2 + s/4 + s/8 + s/16 + = s; where s is the size of the data that is beig broadcast usig tile broadcast operatio.) The commuicatio overhead for steps v) (refer to Sectio IV subsectio C) are all comparable to the overhead associated with step iii). Clearly, the overall commuicatio overhead associated i parallelizig this applicatio is quite miimal whe compared with the processig eeded. It is estimated that the overall executio of this applicatio icludes oly about 5% commuicatio overhead o typical polygo data. It should be oted that we have ot cosidered the time it takes to iitially load the iput polygo data to the master processor sice such time depeds o the iput techology beig used.

7 Because of low commuicatio overhead, this parallel versio of the applicatio is quite scalable (both, algorithmically ad i terms of the umber of processors/odes.) 7. Coclusio The work preseted here described a parallel polygo approximatio algorithm targeted at recofigurable multi-rig hardware. The algorithm is based o mergig priciple ad grows edges simultaeously at locatios where miimum mergig error (local error) is produced. Mergig is carried out i such a way so that both the local ad the global errors are maitaied withi the allowed error. The parallel versio of the polygo approximatio algorithm targeted at recofigurable multi-rig hardware was described. The commuicatio overhead itroduced to parallelize this applicatio is cosidered to be miimal ad is estimated to be about 5% of the overall executio time. Because of low commuicatio overhead, this parallel versio of the applicatio is quite scalable (both, algorithmically ad i terms of the umber of processors/odes.) 8. Refereces [1]. Arabia H. R., "Distributed Stereocorrelatio Algorithm", iteratioal Joural of Computer Commuicatios (Elsevier Sciece), pp , [2]. Arabia H. R., The Trasputer Family of Products ad Their Applicatios i Buildig A High Performace Computer, Ecyclopedia of Computer Sciece ad Techology (A. Ket ad J. Williams, eds.), Marcel Dekker, New York, to appear, [3]. Arabia, Hamid R., ad Thiab R. Taha A Parallel Numerical Algorithm o a Recofigurable Multi-Rig Network. Joural of Telecommuicatio Systems, Vol. 10, pp , [4]. Bhadarkar S. M. ad Arabia H. R., "Parallel Computer Visio o a Recofigurable Multiprocessor Network"; The IEEE Trasactios o Parallel ad Distributed Systems, Vol. 8, No. 3, pp , [5]. Bhadarkar S. M., Arabia H. R. ad Smith J. W., A Recofigurable Architecture for Image Processig ad Computer Visio, Special Issue of Iteratioal Joural of Patter Recogitio ad Artificial Itelligece (IJPRAI) o VLSI Algorithms ad Architectures for Computer Visio, Image Processig, Patter Recogitio ad AI, Vol. 9, No. 2, pp , [6]. Duham, J. G., "Optimum uiform piecewise liear approximatio of plaar curves," IEEE Tras. Patter Aal. Machie Itell., vol. PAMI-8, pp , [7]. Lowe, D. G., "Orgaisatio of Smooth Image Curves at Multiple Scales," I Proc. 2d ICCV, Tarpo Sprigs, FL, pp , [8]. Pavlidis, T., "Waveform segmetatio through fuctioal approximatio," IEEE Tras. Comput., vol c-22, pp , [9]. Pavlidis, T., ad Horowitz, S. L., "Segmetatio of plae curves," IEEE Tras. Comput., vol. c-23, pp , [10]. Pavlidis, T., Algorithms for Graphics ad Image Processig. Spriger Verlag, [11]. Ramer, U., "A iterative procedure for the polygoal approximatio of plae curves, "Comput. Graphics Image Processig, vol. 1, pp , [12]. Roberge, J., "A data reductio algorithm for plaar curves," Comput. Visio, Graphics, Image Processig, vol. 29, pp , [13]. Sklasky, J. ad Gozalez, V., "Fast polygoal approximatio of digitised curves," Patter Recogitio, vol. 12, pp , [14]. Su Yug-Nie ad Huag Shu-Chie, Geetic Algorithms for Error-Bouded Polygo Approximatio, Iteratioal Joural of Patter Recogitio ad Artificial Itelligece, Vol. 14, No. 3, pp , [15]. Suzuki, K., Nishida, Y., ad Hata, S., "A fast polygoal approximatio method for real-time shape recogitio," IEEE Coferece o Patter Recogitio, pp , [16]. Teh, C. ad Chi, R. T., "O the detectio of domiat poits o digital curves," IEEE Tras. Patter Aal. Machie Itell., vol. 11, issue 8, pp , [17]. Wall, K. ad Daielsso, P. E., "A fast sequetial method for polygoal approximatio of digitized curves," Comput. Visio, Graphics, ad Image Processig, vol. 28, pp , [18]. Wai M. Arif ad Pham D.T., "Feature-based cotrol chart patter recogitio", It. J. Prod. Res., 35(7), pp , [19]. Wai M. Arif ad Pham D. T., Efficiet Cotrol Chart Patter Recogitio Through Syergistic ad Distributed Neural Networks, Proceedigs of Mechaical Egieers, Joural of Egieerig Maufacture, pp , vol. 213, part B, [20]. Wai, M. Arif, SAFARI : A Structured approach for automatic rule iductio IEEE Trasactios o Systems Ma ad Cyberetics joural. Vol 31 (4): pp AUG [21]. Wai, M. Arif, ad Batchelor B. G., Edge Regio Based Segmetatio of Rage Images, IEEE Trasactios o Patter Aalysis ad Machie Itelligece, pp , March [22]. Wai, M. Arif, ad Arabia, H. R., Parallel Edge-Regio-Based Segmetatio Algorithm Targeted at Recofigurable Multi-Rig Network,, The Joural

8 of Supercomputig, vol. 25, iss 1, pp , May [23]. Williams, C. M., "A efficiet algorithm for the piecewise liear approximatio of plaar curves," Comput. Graphics Image Procesig, vol. 8, pp , [24]. Wu, L. D., "A piecewise liear approximatio based o a statistical model," IEEE Tras. Patter Aal. Machie Itell., vol. PAMI-6, pp , 1984.