Applicaion Noe MB86297A Carmine Timing Analysis of he DDR Inerface Fujisu Microelecronics Europe GmbH Hisory Dae Auhor Version Commen 05.02.2008 Anders Ramdahl 0.01 Firs draf 06.02.2008 Anders Ramdahl 0.02 Second draf 08.02.2008 Anders Ramdahl 0.03 Third draf 11.02.2008 Anders Ramdahl 1.00 Firs release 1
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0 Absrac This documen describes he iming analysis required o ensure proper operaion of he DDR inerface of he MB86297A 'Carmine' graphics driver from Fujisu. 1 References Referenced documens: CHWRM JESD79E Fujisu, MB86297A Carmine Hardware Reference Manual rev. 1.22, 25 June 2007 JEDEC Sandard, Double Daa Rae DDR SDRAM Specificaion Release E, May 2005 hp://www.jedec.org Addiional informaion: CIBIS CPDG IBIS Fujisu, MB86297A Carmine IBIS Model rev. 1.7 Fujisu, MB86297A Carmine Design Guideline rev. 1.30, 4 June 2007 IBIS I/O Buffer Informaion Specificaion Version 4.2, Raified June 2, 2006 hp://www.eigroup.org All Fujisu documens lised above are available on he Fujisu Graphics Soluions websie: hp://www.fujisu.com/emea/services/microelecronics/displayconrollers/ 2 Definiions 2.1 Naming Convenions In order o disinguish beween he differen iming parameers, he following noaion is used: *DDR DDR SDRAM iming parameer, e.g. DQSCKDDR. The corresponding iming parameer in JESD79E is defined wihou he suffix. * Timing parameer derived from IBIS simulaion of, e.g. CK Timing parameers wihou any of hese suffixes are aken from he CHWRM. Addiionally, minimum and maximum raings are denoed by *MIN and *MAX suffixes. 3
3 Timing Analysis 3.1 Timing Groups In order o simplify he iming analysis, he DDR signals have been divided ino groups wih similar iming characerisics. This allows he iming analysis o be done on he iming groups insead of he individual signals. Figure 1 shows he iming groups in a simplified circui diagram. Table 1 liss which signals belong o which iming group. MB86297A DDR SDRAM CK CMD DQS DQ LOOP Figure 1 Simplified MB86297A o DDR circui diagram Timing Group Signals Commen CK CK, CKn CMD CKE, RAS, CAS, WE, A, BA0, BA1 A refers o all address signals DQS DQS DQ DQ, DM DQ and DM refer o all daa and daa mask signals LOOP LOOP delay compensaion loop of MB86297A. This signal is no par of JESD79E. Table 1 Timing Groups 4
3.2 Delays Due o he high speed naure of he DDR inerface, he delays have o be aken ino accoun during he iming analysis. Figure 2 defines he delays used hroughou his documen. Since i is normally no possible o measure he delays in acual hardware, hese parameers have o be derived from IBIS simulaions. This also has he added advanage of allowing he iming o be checked before any is produced. Since he DQS and DQ groups are bidirecional and he wo chips have differen pad characerisics, he delays have o be derived for boh direcions. Fujisu provides an IBIS model for he MB86297A. The DDR SDRAM manufacurer should provide IBIS models for heir producs. MB86297A DDR SDRAM Figure 2 Delays 5
3.3 Wrie Timing In order o achieve iming closure for wrie operaions, all signals have o arrive a he DDR SDRAM wihin he specified iming condiions. Skew inroduced by he has o be aken ino accoun. For a well balanced design where all he delays are mached, he skew is negligible compared o he available iming margins. If so, he skew can be disregarded. For clariy, he skews have been wrien wihin parenheses in he condiions below. CMD-CK seup and hold iming: > 1 VD seup CMD CMD CK IS DDR MIN + > 2 VD hold CMD CMD CK IH DDR MIN DQS-CK seup and hold iming: + + > 3 Skew DQS CK MIN DQS1 CK CK DQSS DDR MIN + + < 4 Skew DQS CK MAX DQS1 CK CK DQSS DDR MAX In he CHWRM, he seup and hold iming is defined as skew beween DQS and CK insead of seup and hold iming. In order o ranslae hese parameers ino JESD79E conforman ones, a clock period CK has o be added, as seen in 3 and 4. DQ-DQS seup and hold iming: > 5 VD seup DQ DQ1 DQS1 DS DDR MIN + > 6 VD hold DQ DQ1 DQS1 DH DDR MIN 3.4 Read Timing In order o achieve iming closure for read operaions, all signals have o arrive a he MB86297A 'Carmine' wihin he specified iming condiions. DQ-DQS seup and hold iming: + < 7 DQSQ DDR MAX DQ2 DQS 2 SETUP DQ + > 8 QH DDR MIN DQ2 DQS 2 HOLD DQ Due o he definiion of SETUPDQ in he CHWRM, he negaive value has o be used, as seen in 7. As for he wrie iming, he skew of 7 and 8 can be disregarded if he delays of DQ and DQS are well mached. For clariy, he skews have been wrien wihin parenheses in he above condiions. 6
DQS round rip ime: MB86297A DDR SDRAM Figure 3 DQS Round Trip Time and LOOP Round Trip Time 9 CK + DQSCK DDR MIN + DQS 2 > RTT DQS MIN 10 CK + DQSCK DDR MAX + DQS 2 < RTT DQS MAX LOOP Round Trip Time: 11 RTT LBCK MIN < LOOP < RTT LBCK MAX Please noe ha RTTLBCKMIN has a negaive value in he CHWRM. Since he delay is always posiive, he lef par of 11 is always fulfilled. Difference beween LOOP Round Trip Time and DQS Round Trip Time: 12 CK + DQSCK DDR MIN + DQS 2 LOOP > Skew LP CLK MIN 13 CK + DQSCK DDR MAX + DQS 2 LOOP < Skew LP CLK MAX 7
Appendix A Tesed DDR SDRAMs Theoreically, he MB86297A 'Carmine' graphics conroller should work wih any JEDEC-complian DDR SDRAM. Table 2 liss DDR SDRAMs ha have been successfully esed in hardware ogeher wih he MB86297A 'Carmine' Manufacurer Type Size Commen Samsung K4H561638F-UC 16M 16 Used on MB86297A 'Carmine' PCI evaluaion board Table 2 Tesed DDR SDRAMs 8