TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration 2 1
Course Goals Teach digital design for FPGAs EDA tools, Altera DE2 FPGA platform Hands-on work Bring the knowledge level and skill set up to par with finnish students Need-to-know approach Prepare for studying more advanced courses Prepare for M.Sc. Thesis work FPGA design skills often needed in the department s projects, and within industrial companies 3 International Studies 4 2
Course Content Computer-aided digital circuit design using EDA tools Design software: Mentor Graphics' HDL Designer Design fundamentals: Synchronous, hierarchical, and modular design Interfaces, design re-use Modeling digital systems using different design entry methods: schematic capture, truth tables, and state diagrams Design verification: Test benches, simulation Simulation software: Mentor Graphics' ModelSim o Delay simulation Design implementation: Logic synthesis, place & route, FPGA implementation FPGAs: structure and properties EDA tools: Altera Quartus, Mentor Graphics' LeonardoSpectrum o Power, speed, and area optimization and analysis Hardware description language (VHDL) 5 General Info Prerequisites Basics of digital circuits Recommendable: Basic knowledge about digital design and microprocessors Requirements Attendance to all lectures is COMPULSORY. In case you miss any lecture, you need to appear for the oral examination for that lecture. For that, you need to set an appointment for the oral examination with the lecturer by email. Final Examination (carries 50% of final grade) Compulsory computer exercises (carries 50% of final grade) Grading 0-5, based on the exam and exercise project 6 3
Plagiarism Plagiarism Copying of computer exercises from other group member, cheating in examination will result in serious consequences. 7 Personnel Lectures Waqar Hussain o o Room TG313 Email: waqar.hussain@tut.fi Lecture notes will be available on POP Exercises Lasse Lehtonen, Temmu Pitkanen o Email: firstname.lastname@tut.fi All exercise information will be on POP Send your exercises at tkt1426@cs.tut.fi 8 4
Course Schedule Lectures Period 1, 2: o See POP for the exact schedule and the room number Exercises Periods 1, 2 o See POP for the exact schedule and the laboratory number Web: http://www.tkt.cs.tut.fi/kurssit/1426/ Announcements about possible changes will be also emailed to the registered students 9 Course Material Everything available on the course web pages Lecture notes No text book Exercise material EDA tool tutorials Additional material VHDL guides, tutorials, coding rules etc. Extra slide sets (if needed) 10 5
Exercises in Practice Project work: calculator Done alone or in groups of two/three Constructed piece by piece during the weekly exercises Each task must be completed and accepted Final assembly and testing on the last exercise FPGA prototyping on the Altera DE2 platform 11 Exercises in Practice Two weekly exercise sessions in TC417 Person hours for each exercise must be reported Possible to do the exercises on your own PC Instructions given on the course web pages Return deadline for each exercise is listed on the course web pages Exercise return by email Email address given on the exercise web page 12 6
Altera DE2 FPGA Platform Development board Includes an FPGA and lots of peripherals 13 Altera DE2 FPGA Platform 14 7
Digital Design Overview Combinational system design Design views Functionality, Architecture, Implementation Abstraction levels and hierarchy Digital design flow & automation Specification, Design, Verification, Implementation 15 Digital Systems Classification Two main categories Combinational (old name: combinatorial) Sequential Combinational system No memory Output determined only by the current inputs Any system can be designed with two levels of logic Sequential system Contains memory Output is determined by the inputs AND the current state 16 8
Combinational System Specification Specification defines at the highest level: 1. Set of values for the input: input set 2. Set of values for the output: output set 3. Specification of the input-output function This information is always presented independent of the level of abstraction Input/output set definition must also include the data types Example: o Inputs A, B: 8-bit unsigned integer o Output Y: 16-bit unsigned integer EDA tools allow high-level data types such as floatingpoint numbers and enumerated types o Eventually, however, everything will be represented with only ones and zeros 17 Design Example: Half-Adder 18 Specification Inputs A, B: 1-bit unsigned integer Output Y: 2-bit unsigned integer Function: Y = A + B (arithmetic addition, not OR!) Truth table: Karnaugh maps: A B Y 0 0 0 0 1 1 1 0 1 1 1 2 A B = = Boolean equations: Y 1 = AB Y 0 0 00 0 1 01 1 0 01 1 1 10 A B Y 1 Y 0 0 0 0 0 B 0 1 0 1 A 0 1 1 0 0 1 0 1 1 1 0 1 1 Y 1 Y 0 B A 0 1 0 1 1 1 Y 0 = A B + AB = A xor B 9
Design Example: Half-Adder Boolean equations: Y 1 = AB Gate mapping: Y 0 = A B + AB = A xor B = 19 Combinational System Design Any digital system can be designed using this approach! 1. Truth table Relationship between the inputs and outputs Sequential systems must include the current state among the input column, and the next state among the output columns 2. Karnaugh map for each output bit (and for each next state bit on sequential systems) Select as large areas from the map as possible 3. Form Boolean equations from the Karnaugh maps Optimize the equations, if possible 4. Transform the equations into logic gates 20 10
Basic Gates Recap Inverter AND OR NAND NOR XOR NXOR x x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 0 z = x z = x 1 x 0 z = x 1 + x 0 z = ( x 1 x 0 ) z = ( x 1 + x 0 ) z = x 1 x 0 + x 1 x 0 = x z = x 1 1 + x x 0 + x 0 1 x 0 21 Example: HDL 22 Graphical representation (logic gates): x 3 x 2 x 1 x 0 1 2 1 2 3 A B Hardware description language: A 3 <= x 3 AND x 2 ; B 4 <= x 2 AND x 1 AND x 0 ; Z <= A 3 OR B 4 ;...or alternatively: Z <= (x 3 AND x 2 ) OR (x 2 AND x 1 AND x 0 ); 3 4 Intermediate signals do not have to be used, but tometimes they help to clarify the design C z 11
Digital Design Views Architecture Structure Behavior Functionality What are the logical building blocks? How are they organized? What should be done? What is the behavior? What are the physical components? What kind are they? 23 Implementation Physical Characteristics (example) Architecture Number of AND-gates Clock cycles Functionality y = a+b y(t+1) = x(t-1)+y(t) Clock frequency Delay Power consumption Size 24 Implementation 12
What is an Implementation Realization of the desired functionality on the available architecture Direct mapping, one-to-one Architecture is designed to realize the functionality Each functional operation has corresponding realization in architecture Architecture cannot realize any other functionality Example: digital watch Indirect mapping Architecture can realize also other functionalities There is no exactly corresponding physical component for each functional operation o Shared resources, re-used with respect to time Ultimate example: general-purpose processor 25 Example: Custom VLSI Chip Implementation Functionality: z ( ab) c Architecture: Implementation: ASIC Library of basic components (all gate types available) Functionality is the same as the architecture Direct mapping, the smallest unit is gate (transistor) Implementation = connecting building blocks together! 26 13
Example: Discrete Logic Chip Implementation Functionality: z ( ab) c Architecture: Implementation: 74-series discrete logic c b a The smallest unit is chip z 27 Example: FPGA Implementation Functionality: z ( ab) c Architecture: Implementation: FPGA Indirect mapping, the smallest unit is Look-up Table (can perform all basic logic functions) 28 14
Design Views - Problems SW engineer Designs only functionality Experience needed to fulfill e.g. performance requirements Cannot affect the architecture Electronics engineer Designs architecture Functionality = Architecture Cannot understand separation of the two 29 Design Views - Problems Basic digital design courses Exercises must be simple Design often means only architecture design Functionality z ( ab) c Specification (functional specification) = Architecture Design - often still same as functional specification in a graphical notation! 30 15
Abstraction Levels Architecture Processors, memories Registers Gates Transistors Functionality Algorithms Register transfer Boolean expressions Diff. equations Transistor layout Cells Chips Boards 31 Implementation Abstraction Levels in Design Flow High abstraction level Suitable to coarse planning of what is desired Typically in the beginning of the design flow The lower the level, the more detailed the information and the more effort required if something is changed Abstraction levels and design hierarchy can be considered at the same time On this course, the abstraction level is low Register and gate-level 32 16
33 Hierarchy in Digital Design Large designs must be partitioned into blocks to be manageable Compare: SW functions Nobody writes only main function? Example: Z(i) = X(i-1) + Y(i-1) Clock clk Registers Adder Input Module level X(i) xin RX xreg Output addout ADD z Z (a) RY yreg Physical (transistor) level (c) +5V Clock Flip-Flop Logical (gate and flip-flop) level Gates Transistor (b) Design Flow & Hierarchy System Top-down design 1. Bottom-up design Top level N. Hierarchy level Modules Gates and flip-flops 2. Order of design 2. Transistors A B C D Bottom level N. B 1. A C D 34 17
Design Phases 1. Specification Specify input/outputs and their protocols as well as functionality 2. Design Refine the specificaiton, create simulation and implementation models 3. Verification Ensure that models meet the specification 4. Implementation Synthesize the design into target technology and execute on prototype 35 Different Tools for Different Phases 1. SPECIFICATION, DOCUMENTATION Various tools and text-based formats for expressing the design behavior On this course, the specification is always given 2. DESIGN: HDL Designer (Mentor Graphics) A complete design creation environment Makes it possible to instantiate different kind of design files in one top-level design Many description styles, good for education Provides link to simulation and implementation o Push-button simulation, synthesis, and P&R 36 18
Different Tools for Different Phases 3. VERIFICATION: ModelSim (Mentor Graphics) Simulator for digital designs Widely used in the industry Visualizes the behavior via, e.g. wave forms Can communicate with HDL Designer o Interactive simulation and debugging 4. IMPLEMENTION: Quartus (Altera) Quartus implementation flow tasks 1. Synthesize a netlist from the Hardware Description Language source files (from HDL designer) 2. Map and fit the logic elements into the FPGA chip 3. Program the FPGA device 37 2. HDL Designer A design environment allowing a broad range of design styles: Block and gate diagrams (schematic) State diagrams Truth tables Hardware description languages (eg. VHDL) Generates standard VHDL code from the user s block and state diagrams VHDL allows the simulation and synthesis 38 19
2. HDL Designer Design Styles standard VHDL for other tools 1. RTL block diagram 2. state diagram, truth table 3. top-level structural block diagram 4. handwritten VHDL as is 39 2. HDL Designer Design Flow HDL Designer Auto-generated VHDL.sof programming file.edif 40 Simulation results FPGA chip.gdsii ASIC chip 20
2. HDL Designer Main View test Menubar Toolbar asd View selection User logic Project info List of objects 41 Hierarchical Design Hierarchical design and component re-use are extremely powerful methods Same block can be instantiated multiple 1202_s08 times Blocks can contain library sub-blocks details of selected blcok 42 action buttons Blocks defined top-down, components bottom-up, otherwise equal 21
Automated Verification All designs should be automatically verified Ensure that they meet the specification Assistants provide most of the test benches on this course test input testbench testi OK? 43 user s block results 2. HDL Designer in Practice 1. Create a new project and library for your design files 2. Create design files in your library Designs can be used as components simply by dragging and dropping them into the upper level designs re-use and duplication 3. Connect your design into a test bench that generates the inputs and checks the outputs 4. Run ModelSim to simulate the design Correct any problems in your design and re-run ModelSim until the design passes the test bench 5. Run Quartus synthesization and place&route flows 6. Program the FPGA chip with Quartus Programmer 7. Verify design by using the FPGA board 44 22
3. ModelSim Powerful event-based simulator for VHDL (and Verilog) Can automatically use VHDL files generated by the HDL Designer Widely used in the industry Used in several TKT-courses also Simulates only logical behavior (results) Does not know hardware-related issues eg. delays Delays are accurately known only after synthesis, placement, and routing 45 3. ModelSim Main View Manubar and toolbar simulated design and its sub-bloks signals and parameters of selected component simulated waveform (this space can shown other info as well) command prompt and messages will appear into transcript window on the bottom 46 23
3. ModelSim Features Draws a waveform diagram including Inputs Outputs Any internal signal of any design unit Supports different kinds of data representation forms Binary, decimal numbers, ascii data, analog Allows, for example, Searching for events in the waveform Generation of input signals and Manipulation of any signal Adding breakpoints to the VHDL code 47 3. ModelSim - Waveform high-freq signal multibit bus 1-bit signal Monitored signals Values at cursor Cursor line Analog view of bus Time axis 48 24
3. ModelSim in Practice 49 ModelSim works as standalone simulator together with HDL Designer Starting ModelSim from HDL Designer: a) Start from the topmost level including a test bench o Do not have a design block selected! b) Can be started from any design unit as well o However, inputs have to be generated manually o Impractical Always use a testbench to verify designs thoroughly! 4. Quartus Accepts HDL description of a system (VHDL, Verilog) Quartus flow phases 1. Setup 2. Perform RTL synthesis 3. Map basic gates into FPGA logic 4. Place the logic into specific location in chip 5. Route (connect) the logic elements together 6. Provide statistics and analysis results 7. Create a programming file and upload it into the FPGA 50 25